I have a problem with understanding access to the PPU VRAM memory cells. CPU and PPU have separate data busses.
To gain access to the PPU VRAM you have to use registers $ 2006 and $ 2007.
I can easily understand how you can have direct access to this memory.
I am talking about the possibility animate TILE/Graphics on the background.
For example I have a background in graphic inserted in flower, but I would like the leaves of a flower that revolved around the creating an animation.
Animating Spritea WRAM memory is easy, because we have direct access to the RAM memory SPR. But not VRAM.
Sample CHR BGR - TILE's that will be animated in BGR CHR is no. #$10 to #$18
To gain access to the PPU VRAM you have to use registers $ 2006 and $ 2007.
I can easily understand how you can have direct access to this memory.
I am talking about the possibility animate TILE/Graphics on the background.
For example I have a background in graphic inserted in flower, but I would like the leaves of a flower that revolved around the creating an animation.
Animating Spritea WRAM memory is easy, because we have direct access to the RAM memory SPR. But not VRAM.
Sample CHR BGR - TILE's that will be animated in BGR CHR is no. #$10 to #$18