dougeff wrote:
There's also this... MMC5 example..
https://youtu.be/yLiKOePb4bQ(But I don't know how it works).
MMC5 explicitly supports a left-and-right split screen. Both sides have to use the same fine X scroll (PPU hardware limitation), and all existing PCBs are configured to use the same fine Y scroll (although the MMC5 hardware does support differing fine Y scrolls). This doesn't work on some famiclones; the data for the split screen is stored in on-cart memory, and those famiclones can only use the on-mainboard memory for nametables.
Quote:
CHR-ROM bankswitching, have every tile on the non-scrolling side in 8 different banks, each 1 pixel lower than the last. Every 8 pixels of scroll, you will have to realign the non-scrolling side down 1 tile. This would limit you to a region of about 100 tiles that need to be drawn on a given frame.
If we're just talking about pipe dreams, "all" you need is some spare CHR bank register bits to feed through a Full Adder. Each 1 KiB bank (if you did) could be configured to be a 1x64 / 2x32 / 4x16 / 8x8 / …64x1 tile region with an independent fine Y scroll. (PPUA[0,1,2,4,5,6,7,8] + fine Y offset = ROMA[0,1,2,4,5,6,7,8])
Similarly, if you had a 16-bit-wide ROM for CHR and a barrel shifter, you could get an independent 3 bits of fine X for any given tile. (PPUD[0..7] = bitslice(X offset, ROMD[0..15])
Both of these are basically identical to the standard "use one CHR ROM bank for each possible phase offset of what's onscreen", just taking advantage of a hardware assist to be able to use a lot less memory for tiles.