SusiKette wrote:
By the way is there an actual explanation on why doing this eliminates the conflict and what issues you could run into if you don't handle the bus conflict, for both PRG and CHR (although UNROM doesn't have these) if the issues differ?
The bus conflict occurs because the ROM isn't disabled by the write signal (saves some wiring to have it enabled only by PRG A15, i.e. when the address is >= $8000), so at the moment of the write you have your storing value from the CPU on the bus, but also the value output from the ROM.
With two signals on the bus like this, one or the other "wins" or some other behaviour occurs depending on properties of their circuits. If both are the same, though, it doesn't matter which one wins, because both have the correct value.
That value goes from the bus to a latch on the chip that controls the banking.
You can have bus conflicts with either PRG or CHR banking, it doesn't matter
what you're banking though, it matters
where the register you're writing to is. If the register is at $8000-FFFF, that overlaps with PRG. (I think theoretically you could have a bus conflict with CHR while writing through $2007, but this is a bit obscure, mapper registers are usually in CPU space not PPU.)
They basically did this because it saves one extra component to disable the PRG-ROM during writes. With ASIC mappers it was easier to add the extra logic, so they typically don't have bus conflict problems.