This thread is already confusing, as
ABSOLUTE INDEXED has been described by Memblers: I'm going to reference documentation for that addressing mode just to make it crystal clear:
https://github.com/eteran/pretendo/blob ... .txt#L1092 -- pay very close attention to lines 1145/1146 and the paragraph at 1151-1154.
What you're wanting to comprehend, I believe, are called "T-states" (timing states), where you can understand what the CPU is doing during each cycle of opcode execution.
This document outlines most of those pretty well, but you need to be careful and read it very slowly as it's easy to mistake where you are in the document or what you're reading about. They are not just copy-pastes of the same thing over and over!
Now let's focus entirely on indexed indirect, e.g.
($c0,x), like you asked:
https://github.com/eteran/pretendo/blob ... .txt#L1183Both reads and writes with indexed indirect, e.g.
lda ($c0,x) and
sta ($c0,x), take 6 cycles. Indexed indirect "ignores" page boundaries (thus the potential +1 cycle penalty) because the effective address calculated is always within zero page, i.e.
ldx #$80 / lda ($c0,x) will not load from $140 but from $40. The same applies to
sta ($c0,x).
Indirect indexed, e.g.
($c0),y is different, but only on reads (e.g.
lda), where there can be a +1 cycle penalty if there's a page wrap (thus 6 cycles instead of 5). On writes (e.g.
sta), the cycle count is always 6.
Be prepared for lots of fun when dealing with RMW instructions, e.g.
inc.
If you're asking "why" in the sense of "why was the 6502 designed this way" or "why does this addressing mode differ in behaviour than the other", then you should redirect your question to
Bill Mench, one of the creators of the 6502; you can ask him
here.