I'm having trouble understanding how we can have a PRG block begin at $8000, yet this is also a control register for MMC3 (assuming of course that our ROM specifies MMC3). What am I missing?
Mapper hardware registers can be mapped onto PRG-ROM space in CPU memory because of what it is: read-only memory, with mapper hardware access usually limited to write-only. So, you can read data from a ROM in the same space that you write register values to, because they go to different circuitry.
In the case of MMC3, the MMC3 chip itself will decode adress and will route the CPU to the ROM when reading $8000 and route it to it's internal register when writing to $8000 (while disabling the ROM), so it causes no problem.
In the case of simpler mappers (74HC161 based for example), this "routing" is only parially done. When reading from $8000 it reads the ROM but when writing to it it "writes" both to the ROM and the register. For that reason, the ROM should contain the same data as the write, else bad things will happen (the ROM will output a different logic level than the CPU and both will be in conflict).
Ok, that makes sense, thanks. I thought that must be the case. Perhaps some mention of that should be made in mapper docs or on the wiki, newbies might be completely thrown for a loop by that.