DogP has mailed me the NSS pinout (plus some info on connector names, supply pins, and slot selection). First of, here's the pinout, this confirms the known pins & guessed pins & solves the missing pins:
Attachment:
NSS_Pinout_by_DogP.jpg [ 107.57 KiB | Viewed 1271 times ]
The P_xxx pins are SNES Program ROM, the I_xxx pins are INST ROM, the S_xxx pins are Security PROM, of which, the S_CE pin is a bit far away from the other PROM pins (no idea why Nintendo did arrange like that), and it should be actually called /S_CE (as it's active low, according to RP5H01 datasheet).
In plain ASCII, the pin-out should look as so:
Code:
Cartridge Slots (3 slots, 2x50pin each)
Solder side Component side
A B
WRAM.64 GND - 1 - VCC2 INST.28 ;\
WRAM.64 GND - 2 - VCC2 INST.28 ; PROM
PROM.7-R3 PROM.RES - 3 - PROM.CLK PROM.6 ; (and SNES
PROM.5-R2 PROM.TST - 4 - PROM.CNT PROM.8 ; select)
/SNES_# - 5 - PROM.DTA PROM.1 ;/
INST.15 D3 - 6 - D4 INST.16 ;\
INST.13 D2 - 7 - D5 INST.17 ;
INST.12 D1 - 8 - D6 INST.18 ;
INST.11 D0 - 9 - D7 INST.19 ;
INST.10 A0 - 10 - /CE_# INST.20 ;
INST.9 A1 - 11 - A10 INST.21 ; INST ROM
INST.8 A2 - 12 - /OE INST.22 ;
INST.7 A3 - 13 - A11 INST.23 ;
INST.6 A4 - 14 - A9 INST.24 ;
INST.5 A5 - 15 - A8 INST.25 ;
INST.4 A6 - 16 - A7 INST.3 ;
INST.2 A12 - 17 - GND WRAM.64 ;
WRAM.64 GND - 18 - VCC2 INST.28 ;
WRAM.64 _______ GND - 19 - VCC2 ______ INST.28 ;/
WRAM.64 GND - 20 - VCC WRAM.1 ;\
WRAM.64 GND - 21 - VCC WRAM.1 ;
WRAM.56 /PARD - 22 - /PAWR WRAM.58 ;
WRAM.47 PA6 - 23 - PA7 WRAM.50 ;
WRAM.45 PA4 - 24 - PA5 WRAM.46 ;
WRAM.43 PA2 - 25 - PA3 WRAM.44 ; SNES Bus
WRAM.53 PA0 - 26 - PA1 WRAM.54 ; (and PROM
WRAM.57 /RD - 27 - /WR WRAM.59 ; select)
WRAM.63 D3 - 28 - D4 WRAM.2 ;\D4..D7 in ;
WRAM.62 D2 - 29 - D5 WRAM.3 ; opposite ;
WRAM.61 D1 - 30 - D6 WRAM.4 ; order as ;
WRAM.60 D0 - 31 - D7 WRAM.5 ;/on SNES ;
CPU.46 /IRQ - 32 - /ROMSEL CPU.77 ;
CPU.93 A0 - 33 - A23 CPU.17 ;
CPU.94 A1 - 34 - A22 CPU.16 ;
CPU.95 A2 - 35 - A21 CPU.15 ;
CPU.96 A3 - 36 - A20 CPU.14 ;
CPU.97 A4 - 37 - A19 CPU.13 ;
CPU.98 A5 - 38 - A18 CPU.12 ;
CPU.99 A6 - 39 - A17 CPU.11 ;
CPU.100 A7 - 40 - A16 CPU.10 ;
CPU.2 A8 - 41 - A15 CPU.9 ;
CPU.3 A9 - 42 - A14 CPU.8 ;
CPU.4 A10 - 43 - A13 CPU.7 ;
CPU.5 A11 - 44 - A12 CPU.6 ;
WRAM.7 REFRESH - 45 - /WRAMSEL WRAM.15 ;
AUDIO_L - 46 - AUDIO_R ;
PROM.2 PROM./CE_# - 47 - SYSCLK WRAM.6 ;
CPU.48 MCK 21M - 48 - /RESET WRAM.8 ;
WRAM.64 GND - 49 - VCC WRAM.1 ;
WRAM.64 GND - 50 - VCC WRAM.1 ;/
The NSS motherboard uses female Matsushita AXD100271 connectors, and the NSS
cartridges have male Matsushita AXD200251 connectors. Both are obsolete as of a
few years ago, but they're just shrouded 0.1" headers.
All pins are same on all three cartridge slots, except three pins have separate signals per slot:
A47: PROM./CE_# = PROM chip enable for slot 1,2,3 (can be directly wired to PROM)
B10: INST./CE_# = INST ROM chip enable for slot 1,2,3 (can be directly wired to EPROM)
A5: /SNES_# = SNES enable for slot 1,2,3 (must by manually ORed with /ROMSEL (and other pins if needed))
For the supply pins, B17 is actually GND (including on mainboard side). And for VCC pins: The Z80 supply (for INST ROM and PROM) is always powered, and the SNES supply can be switched off (via Q1 transistor on mainboard) (whatever that is good for, it might save some energy during menu selections, but during Demo mode the SNES supply needs to be certainly enabled).
About the /SNES_# signal (pin A5), basically this should be ORed with the SNES read/write/chip_select signals. Instead of using an OR gate, the NSS cartridges are usually doing this by using 74HC367 tri-state buffer (similar as PC10 carts), this chip could switch up to 6 signals (which may be actually required for some cartridges), but in normal NSS carts it is merely switching one single signal (/ROMSEL); wired as so: Pin1=/SNES_#, Pin2=/ROMSEL_IN (from NSS), Pin3=/ROMSEL_OUT (to cartridge; with pull-up resistor), all other inputs are GNDed, and all other outputs are NC.
Aside from /ROMSEL, it may be also required to switch /RD, /WR, /PARD, /PAWR, and in opposite direction: /IRQ. Together with the /ROMSEL signal, this could be done neatly via the six channels of the 74HC367 chip (plus six pull-up resistors).
/RD and /WR would be required for cartridges that do memory mapping without /ROMSEL=LOW (that would be: SRAM in HiROM carts, the NSS DIP switch cartridges, and several SNES coprocessor carts which do leave /ROMSEL completely unused).
/PARD and /PAWR would be needed only for making a 100% functional SNES adaptor (though in practice there aren't any SNES cartridges known to use that signals).
/IRQ might be required for some cartridges. If the cartridges do disable /IRQ upon /RESET, and if they do produce open-collector /IRQ signals then it wouldn't be required to disable /IRQ on deselected cartridges. But I've no idea if the existing SNES cartridges are really working like so (or maybe some do, and others don't). So it may be better to switch /IRQ by passing it through the 74HC367 (in opposite direction as the other signals, and with a pull-up resistor on the
cartridge side (the resistor would be required for cartridges that
do use open-collector /IRQ outputs) (for the NSS mainboard side: there should be already a pull-up resistor present, at least it's like so on SNES mainboards).
EDIT: A fully functional NSS-to-SNES-cartridge adaptor would also require a CIC chip (as a few SNES cartridges with special protections won't work if the 'console' doesn't output the correct CIC signals).
Accordingly, the adaptor would also need something that generates the 3.072MHz CIC clock signal (on a real SNES that would be 24.576MHz/8 coming from APU) (on the NSS adaptor it would require a separate oscillator, or if accuracy doesn't matter, then one might get away with 21.xxxMHz PAL/NTSC master clock divided by 7 (or dirtier: divided by 8)).
Unless there should be another way to get those protected cartridges to work (maybe by simply wiring CIC clock to VCC or GND, or by feeding it only a few dozen of CIC clks after reset, so it could initialize itself, but would never reach the point where the protection could do something harmful).