If I use a low voltage flash rom in standard Snes carts, is the 3.3 volts output on the data lines high enough to drive the Snes data lines? In other words, do I need a level translator up converter or can I tie the outputs directly to the Snes data lines?
I'm using a level translator on the address inputs.
Thanks!!!
You just want to know if you don't need to level shift the D0-D7 outputs? I guess to save having to do it if you don't need to? I'm not an expert on it but I think it would work, not shifting the output signals to 5v levels. But all the inputs to the chip certain need to be level shifted down if the chip isn't 5v tolerant. But I think you knew that. I don't think you'd be at risk hurting anything by leaving the data output pins as-is. I think the worst that could happen is it just not working by not thinking 3.3v is enough for high logic level. But I think it is. Some people I think have used 3.3v flash chips without level shifters directly in SNES carts and they work until the 5v input frys the chip. So the logic level should probably be ok. But I'd wait till someone else chimes in.
The SNES CPU can still drive the data bus to 5V high, say for writing to SRAM, or anything that uses the shared data bus for that matter (WRAM?), potentially damaging the data lines if they aren't 5V tolerant. I'd use a level shifter.
qwertymodo wrote:
The SNES CPU can still drive the data bus to 5V high, say for writing to SRAM, or anything that uses the shared data bus for that matter (WRAM?), potentially damaging the data lines if they aren't 5V tolerant. I'd use a level shifter.
But isn't the rom chip disabled (CE held Hi) when SRAM is enabled? Or did I get that wrong?
Even if the ROM chip's address decoder (/CE) or output (/OE) is not asserted, the +5 V from the data lines can still power the chip through the internal protection diode on each input pin.
tepples wrote:
Even if the ROM chip's address decoder (/CE) or output (/OE) is not asserted, the +5 V from the data lines can still power the chip through the internal protection diode on each input pin.
Humm. That is concerning. Thanks for everyone's input.
I too thought that maybe because it was not active it might be protected. It seems that's not the case then.
Even if the chip is disabled, the CPU will still assert the data bus any time it tries to write to any device on that bus and those devices will assert the bus any time it reads from them, resulting in +5V on those pins (for high bits), whether the chip is enabled or not, powered or not, it doesn't matter, the voltage is still there, and if it can't tolerate +5V on the data pins, you could blow them.
Ok. VERY good points! I hadn't considered the other devices writing to the bus.
Let me switch gears on this....
Has anyone scoped the voltages on the bus? Do they really peak at 5v or is is 4.xx? I know the inputs on the flash rom are not 5v tolerant but they are pretty close to 4 volts .
Also, a different gear, in the post
viewtopic.php?f=12&t=4877 where a 42 pin EPROM (16bit) that uses either the 245 ic's or the 257 ic's, would these ic's provide isolation (or protection) of the flash roms data bus --- this supposes that instead of the big 42 pin EPROM, a LV flash rom is used instead.
That would work, but only if you used 3.3V Vcc, which may or may not properly drive the logic high to the rest of the 5V system, and at that point, you might as well just use a level shifter...
What I was wanting to do was to have my cake and eat it too.
I was Looking at using a 42 pin EPROM 27c322 (16 bit only) that would be socketed. So for regular run of the mill games, I could use a 27c322 or for bigger games (or multi games on 1 rom) I would use an adapter that is
similar to the tsop40 to 36dip adapter but it would be a tsop56 to dip48 "adapter". Even though some of the flash roms are capable of 8 bit mode, the dip42 EPROM (27c322) is 16bit only. So I was going to keep everything 16 bit for uniformity. But the flash roms are all 3.6. Volts with pin tolerances of 4.1 volts -- which is why I was wondering what the
actual peak voltage on the data bus.
I think you are right, I'll just have to add another level shifter. Chip count was getting tight in the available space which is why i was wondering if I could run the data lines without a level shifter.
Thanks for everyone's inputs.
A lot of 5V parts can run just fine at 3.3V, and whatever voltage you give it on Vcc will determine the logic-high voltage of the I/O, so for your "universal" socket, just go full 3.3V with a logic level shifter between it and the cart bus.
Edit: this may not be true for older EEPROMs, check the datasheets, but a lot of modern memory chips have a decently wide operating Vcc range.
Has anyone experimented with running all of the SNES's logic on 3.3V?
Maybe infinitelives would know. I think his board is 3.3 (at least the flash rom is.....)