I've mentioned this idea a couple of times in other contexts, but it didn't generate any discussion, and I'm kinda curious about whether I'm right. I might even need it, although I'm still hoping I won't...
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As we know from the adventures of Drakon and his trusty glue gun, Super FX chips can be overclocked a fair bit. Of course, the practical limit varies between units, and in any case it seems unlikely that Nintendo would have approved of a licensed developer attempting to deploy a 60 MHz MARIO Chip 1. But what if a GSU2 could be overclocked in a way that left it completely within spec?
If bus access time for the Super FX reflects the memory speed in the same way as the timing of the second half-cycle of the S-CPU's bus access, then the five-cycle byte access time in fast mode implies the use of 200 ns memory. The fact that Super FX games are invariably described as SlowROM lends some weight to this assumption. It would seem to make sense that the use of cheaper memory would have been assumed in connection with an expensive coprocessor, especially early in the console's life when the Super FX was being developed.
But there doesn't seem to be a FastROM variant of the Super FX. With 120 ns memory, if my assumption above is accurate, bus access could be reduced to three cycles per byte in fast mode, which would substantially speed up blitting, texture mapping, RAM reads, and really just about anything that uses the external buses heavily enough for the access time to be a bottleneck. Unfortunately it seems this was never done.
Here's the thing: in slow mode (nominally 10.7 MHz on a 21.4 MHz crystal), bus access is three cycles per byte rather than five, and as far as I know that's the only timing difference between the modes. So why not simply leave the chip in slow mode, with fast multiply turned off, and feed it a 42.8 MHz clock signal? That should give you a 21.4 MHz Super FX chip with 3-cycle bus access, right? And if you were to use 120 ns ROM and SRAM, everything (except possibly the clock divider?) would be within spec.
Am I missing something?
...
As we know from the adventures of Drakon and his trusty glue gun, Super FX chips can be overclocked a fair bit. Of course, the practical limit varies between units, and in any case it seems unlikely that Nintendo would have approved of a licensed developer attempting to deploy a 60 MHz MARIO Chip 1. But what if a GSU2 could be overclocked in a way that left it completely within spec?
If bus access time for the Super FX reflects the memory speed in the same way as the timing of the second half-cycle of the S-CPU's bus access, then the five-cycle byte access time in fast mode implies the use of 200 ns memory. The fact that Super FX games are invariably described as SlowROM lends some weight to this assumption. It would seem to make sense that the use of cheaper memory would have been assumed in connection with an expensive coprocessor, especially early in the console's life when the Super FX was being developed.
But there doesn't seem to be a FastROM variant of the Super FX. With 120 ns memory, if my assumption above is accurate, bus access could be reduced to three cycles per byte in fast mode, which would substantially speed up blitting, texture mapping, RAM reads, and really just about anything that uses the external buses heavily enough for the access time to be a bottleneck. Unfortunately it seems this was never done.
Here's the thing: in slow mode (nominally 10.7 MHz on a 21.4 MHz crystal), bus access is three cycles per byte rather than five, and as far as I know that's the only timing difference between the modes. So why not simply leave the chip in slow mode, with fast multiply turned off, and feed it a 42.8 MHz clock signal? That should give you a 21.4 MHz Super FX chip with 3-cycle bus access, right? And if you were to use 120 ns ROM and SRAM, everything (except possibly the clock divider?) would be within spec.
Am I missing something?