Sour wrote:
during rendering (scanline -1 to 239), the PPU puts the address it needs to fetch the data on the bus
Yes.
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, and any register writes will directly set the bus to that address (but the PPU's next fetch will be affected by the new value)?
Typo? I assume you mean "will not directly set"
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When scanline 240 begins (or when rendering is turned off), the bus returns to the current value of "VRAMAddr" and keeps that value until the prerender line? (unless changed by register writes)
I believe that's accurate.
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So, because the bus' value is controlled by the PPU during rendering, and the PPU never fetches anything in the $3000+ range, it's impossible to write to the palette during this time. Whereas writes to $0000-$2FFF via $2007 are possible, but will (almost?) never write to the correct address, because writing to $2006 during rendering will update VRAMAddr, but will not have an immediate impact on the bus' current value (but it will have an impact on the bus' value the next time the PPU reads VRAMAddr to fetch a byte for rendering purposes)?
That also sounds accurate.
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Quickly tracking down the PPU A8 signal in Visual2C02...
* It's synchronized on left half dots (t13798)
There's a five-way analog multiplexer behind this, selecting between
* Vcc during attribute fetches = node 1162 (+hpos_eq_0-255_or_320-335_and_hpos_mod_8_eq_2_or_3_and_rendering)
* vramaddr_+v8 during node 2047 (must be used for both nametable fetches and the inactive portion)
* node10730 during node 1275 (node 10730 is just a floating node... node 1275 is part of the "CPU writes to $2007" handler)
* node 9110 during node 1963 = pattern table fetch
** Node 9110 ultimately comes from another multiplexer,
** ultimately spr_d4, after nodes 1870, 328 (++hpos_eq_256_to_319_and_rendering), and a right half dot
** ultimately _db4, after a right half dot, and nodes 1870 and 1910 and another (the same) right half dot
In contrast, PPU A13 (still synchronized on left half dots) only has a two-way analog multiplexer, selecting between
* Ground during node 1963 (pattern table fetch)
* node 2042 during node 2047 or attribute fetches (1162)
** node 2042 is ultimately OR(vramaddr_+v13 , rendering_1)
PPU A12 is the one that does all the dirty work, because it has to be able to operate in the most different ways.
bkg_pat_out, spr_pat_out, spr_d0 (8x16 mode), NOR(vramaddr_/v12, rendering_1)
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oh. ... huh, the timing glitches we saw on [$2000] & 3 or writes to $2005 and $2006 should also happen to [$2000] & $38, but only for a single sliver.