Hi there,
I've had yet another idea to cram more into my DMC IRQ-based PCM music player, since a scheduler meant to handle game logic tasks during a wait inside the IRQ handler proved to be of very little added efficiency to a game. Since I need to wait more than 100 cycles / IRQ, I thought I could use a trick to continously reset the phase of a pulse channel by writing the high period register to continously output the first 1-step of the 75% duty waveform, letting me use the channel as a 4-bit DAC via the volume register. I would use this to play sound effects without having to software mix them with the music being played via $4011.
However, while the wave sequence is reset when the write happens, the timer is not from what I gather? That of course means that no matter what, I will get a "cut" in the sound every 2049 APU cycles (when the divider underflows and reloads from the period), which when aligned the worst, should persist for the time between two phase resets. This should be 432 CPU cycles, or possibly more (432 + 512 ± 1) if an OAM DMA happens to block the IRQ at the worst possible time as well.
Is there any way to ensure that the waveform remains completely flatlined, volume changes excluded (e.g.: by changing back-and-forth between two duty cycles at the precise moment) to make this work without added distortion?
I've had yet another idea to cram more into my DMC IRQ-based PCM music player, since a scheduler meant to handle game logic tasks during a wait inside the IRQ handler proved to be of very little added efficiency to a game. Since I need to wait more than 100 cycles / IRQ, I thought I could use a trick to continously reset the phase of a pulse channel by writing the high period register to continously output the first 1-step of the 75% duty waveform, letting me use the channel as a 4-bit DAC via the volume register. I would use this to play sound effects without having to software mix them with the music being played via $4011.
However, while the wave sequence is reset when the write happens, the timer is not from what I gather? That of course means that no matter what, I will get a "cut" in the sound every 2049 APU cycles (when the divider underflows and reloads from the period), which when aligned the worst, should persist for the time between two phase resets. This should be 432 CPU cycles, or possibly more (432 + 512 ± 1) if an OAM DMA happens to block the IRQ at the worst possible time as well.
Is there any way to ensure that the waveform remains completely flatlined, volume changes excluded (e.g.: by changing back-and-forth between two duty cycles at the precise moment) to make this work without added distortion?