Just some comments about the questions on your "emulation accuracy" page.
Quote:
What happens if the CPU accesses memory during OAM DMA?
I believe someone tested this and found that on the DMG, reads (presumably including opcode fetches) return the byte currently being DMAed. On the GBC, external WRAM (i.e. $C000-$DFFF) is on a separate physical bus from the cartridge slot, probably because of the WRAM bankswitching. If you read WRAM during DMA it has the same effect as on the DMG, but you can apparently run code from ROM normally while DMAing from WRAM (the Wizardry Famicom remakes do this--they don't bother copying their OAM DMA routine to $FF80) There are probably some limitations to executing code in parallel with DMA; the Wizardry games still do a 160-cycle delay loop after triggering DMA.
I've never seen any test results for writes during OAM DMA, or whether OAM DMA automatically suppresses interrupts.
Quote:
What is the exact behaviour of EI?
On a real Z80 (and I believe an 8080 as well), "EI's effect is delayed one cycle" is not true so much as "EI actually
disables interrupts until after the next instruction" The reason is to ensure that the sequence "EI; RET" is atomic. If you put a hundred EIs in a row, no interrupts can occur between any of them. You should test whether this is true on the GB as well.
On a real Z80, prefix instructions are the same: no interrupt can occur between the prefix and the instruction it's modifying (the 8080 doesn't have any prefix instructions). This is almost certainly true on the GB as well, otherwise chaos would ensue (you could never safely use a CB instruction any time an interrupt could possibly happen)
Quote:
What is the exact timing of PUSH rr?
It's not surprising that PUSH has an extra internal delay that POP doesn't. Remember that the GB, like other 8080-family CPUs, has a "full" stack: SP points to the last item pushed. So PUSH has to decrement SP first to generate the address for the write, whereas POP can immediately read memory while incrementing SP in parallel. The 6502 family has an "empty" stack, and pops take one more cycle than pushes do--exactly the opposite of the 8080 family.
Quote:
What does MBC1 do if you request a ROM bank number higher than what the cartridge supports?
MBC1 only has five data pins; it can't see the top three bits of the data bus at all. That's why ROMs bigger than 4 MBit need a second register to select the upper bank bits. So a data value of 32 will mirror to 0
in the MBC and trigger the "0 actually selects 1" behaviour, but a data value of 16 on a 2 Mbit ROM, or 8 on a 1 Mbit ROM will mirror to 0
in the ROM and won't be converted to 1. The MBC doesn't "know" how big the ROM is; smaller ROMs just leave the upper address lines of the MBC unconnected.
Likewise MBC2 only has four data pins; that's why its internal battery RAM is arranged in nybbles, and why it only supports up to 2 Mbit ROMs.
Also, MBC1 is only connected to A15, A14 and A13 of the cartridge bus, and MBC2 is only connected to A15, A14 and A8-A0. So MBC1 registers are mirrored over spans of $2000 bytes, and MBC2 registers are mirrored over spans of $100 bytes (you can select a ROM bank by writing to $0100-01FF, $0300-03FF, $0500-05FF, etc.) The reason most monochrome GB games write to $2100 to switch ROM banks is to be compatible with either MBC1 or MBC2.
re those bus timing diagrams: in case it isn't obvious, the reason why accesses to $8000-9FFF don't show any bus activity is that VRAM is on a separate bus on the GB (on the 'Pocket and everything afterwards it's built right into the CPU)
DMG:
13-bit address bus and 8-bit data bus to VRAM
16-bit address bus and 8-bit data bus to WRAM and the cartridge slot
$FF80-FFFE internal to the CPU
GBP:
Unconnected external VRAM address and data bus (maybe it can be enabled and the internal VRAM disabled somehow?)
16-bit address bus and 8-bit data bus to WRAM and the cartridge slot
VRAM and $FF80-FFFE internal to the CPU
GBC:
15-bit address bus and 8-bit data bus to WRAM (the upper 3 bits come from the bank select register)
16-bit address bus and 8-bit data bus to the cartridge slot only
VRAM and $FF80-FFFE internal to the CPU
GBA:
WRAM moved inside the CPU as well. The only external RAM on the GBA is the big slow work RAM (which isn't usable in GBC mode)
Schematics showing pinouts of the GB CPU, MBC1 and MBC2 are at
http://fms.komkon.org/GameBoy/Tech/Hardware.html