whicker wrote:
It's fairly rare on other CPUs, but the 68K series has an input pin called DTACK (active low).
DTACK = data acknowledge.
If memory or a peripheral isn't ready for a read or write, it simply doesn't assert DTACK and the CPU will just wait.
The 6502 has that as well for reads, where pulling RDY (ready) low during a read halts the CPU until it returns high. This is what the DMA controllers on the 2A03 (NES CPU) and 5A22 (S-CPU) do to stop execution.
Quote:
I miss the 68K. It made so much sense. (Except for bombing out on unaligned address accesses).
One could write an exception handler that emulates unaligned access, just as one writes a handler for the "Fxxx instruction" that emulates some model of FPU. But then an unaligned access more likely indicates a corrupt pointer, much as a bus error does.