Hi erverybody
I'm currently trying to develop a FPGA-Implementation of a NES and i need your help understanding the timing between the CPU and the PPU.
Let's say i write to PPUDATA (sta $2007), having PPUADDR at $00 and PPUCTRL.2 at 0, the CPU puts 2007 on the address-bus and set the ChipSelect-Pin for the PPU. Since the PPU runs 3 times faster than the CPU, the CS-Pin is low for 3 PPU-Cycles. But when i read from VRAM on every PPU-Cycle and increment PPUADDR according to PPUCTRL.2 when /CS is low i will get the totally wrong behavior (an increment by 3). How does the actual PPU work that it increments PPUADDR only one time when the signals at the address-bus and the /CS-Pin stay for more than 1 cycle?
Am i going right that every 3rd rising edge of the PPU-Clock is in sync with the rising edge of the CPU-Clock?
Greetings
Chris
I'm currently trying to develop a FPGA-Implementation of a NES and i need your help understanding the timing between the CPU and the PPU.
Let's say i write to PPUDATA (sta $2007), having PPUADDR at $00 and PPUCTRL.2 at 0, the CPU puts 2007 on the address-bus and set the ChipSelect-Pin for the PPU. Since the PPU runs 3 times faster than the CPU, the CS-Pin is low for 3 PPU-Cycles. But when i read from VRAM on every PPU-Cycle and increment PPUADDR according to PPUCTRL.2 when /CS is low i will get the totally wrong behavior (an increment by 3). How does the actual PPU work that it increments PPUADDR only one time when the signals at the address-bus and the /CS-Pin stay for more than 1 cycle?
Am i going right that every 3rd rising edge of the PPU-Clock is in sync with the rising edge of the CPU-Clock?
Greetings
Chris