Hi everybody
My logic level converter board is complete and im able to connect a gamepak with my FPGAnes.
Currently im figuring out how to control the address and data buses to get the rom data into my CPU.
I observed that the CPU databus only has a value while /ROMSEL is low (and CPU_RW is high of course)
, whereas i'm used to have a value read from memory for the whole duration of the next cycle inside of
my FPGA. I don't think this is a problem to me, just adding a flip flop which updates permanently with
the databus value while /ROMSEL is low but i wonder how the real CPU (and PPU) is doing this job.
Has the CPU/PPU something similar or do i simply miss something?
Chris
My logic level converter board is complete and im able to connect a gamepak with my FPGAnes.
Currently im figuring out how to control the address and data buses to get the rom data into my CPU.
I observed that the CPU databus only has a value while /ROMSEL is low (and CPU_RW is high of course)
, whereas i'm used to have a value read from memory for the whole duration of the next cycle inside of
my FPGA. I don't think this is a problem to me, just adding a flip flop which updates permanently with
the databus value while /ROMSEL is low but i wonder how the real CPU (and PPU) is doing this job.
Has the CPU/PPU something similar or do i simply miss something?
Chris