Hello.
I've made some progress with my 6502 emulator and it runs nestest like a charm, except for the PPU dots. I'm trying to adjust the timing of the instructions (taking into account 1 CPU cycle = 3 dots). I have a problem with this instruction:
The problem here is the log shows the STA instruction should take 6 cycles. However, STA only takes 6 cycles when page boundary is crossed : http://atarihq.com/danb/files/64doc.txt
There isn't page boundary crossing this time (since Y = 0). So, why does the log state the instruction should take 6 CPU cycles?
I've made some progress with my 6502 emulator and it runs nestest like a charm, except for the PPU dots. I'm trying to adjust the timing of the instructions (taking into account 1 CPU cycle = 3 dots). I have a problem with this instruction:
Code:
DB65 91 33 STA ($33),Y = 0400 @ 0400 = 7F A:87 X:06 Y:00 P:E5 SP:FB CYC:239
DB67 AD 00 04 LDA $0400 = 87 A:87 X:06 Y:00 P:E5 SP:FB CYC:257
DB67 AD 00 04 LDA $0400 = 87 A:87 X:06 Y:00 P:E5 SP:FB CYC:257
The problem here is the log shows the STA instruction should take 6 cycles. However, STA only takes 6 cycles when page boundary is crossed : http://atarihq.com/danb/files/64doc.txt
Code:
Indirect indexed addressing
Read instructions (LDA, EOR, AND, ORA, ADC, SBC, CMP)
# address R/W description
--- ----------- --- ------------------------------------------
1 PC R fetch opcode, increment PC
2 PC R fetch pointer address, increment PC
3 pointer R fetch effective address low
4 pointer+1 R fetch effective address high,
add Y to low byte of effective address
5 address+Y* R read from effective address,
fix high byte of effective address
6+ address+Y R read from effective address
Notes: The effective address is always fetched from zero page,
i.e. the zero page boundary crossing is not handled.
* The high byte of the effective address may be invalid
at this time, i.e. it may be smaller by $100.
+ This cycle will be executed only if the effective address
was invalid during cycle #5, i.e. page boundary was crossed.
Read instructions (LDA, EOR, AND, ORA, ADC, SBC, CMP)
# address R/W description
--- ----------- --- ------------------------------------------
1 PC R fetch opcode, increment PC
2 PC R fetch pointer address, increment PC
3 pointer R fetch effective address low
4 pointer+1 R fetch effective address high,
add Y to low byte of effective address
5 address+Y* R read from effective address,
fix high byte of effective address
6+ address+Y R read from effective address
Notes: The effective address is always fetched from zero page,
i.e. the zero page boundary crossing is not handled.
* The high byte of the effective address may be invalid
at this time, i.e. it may be smaller by $100.
+ This cycle will be executed only if the effective address
was invalid during cycle #5, i.e. page boundary was crossed.
There isn't page boundary crossing this time (since Y = 0). So, why does the log state the instruction should take 6 CPU cycles?