having a problem with Castlevania2, i start the game and walk down the stairs and there are frame glitches were the starting ppu address is 0 randomly. i have traced the ppu address and it increments except for the few glitches were it starts a 0.
i have checked nmi's and those are every frame, nothing that looks wrong.
i think i might have the ppu address and ppu address latch wrong. usually the code before every frame while in the town is writing to the ppu and setting the ppu address. on the frames with glitches it does nothing, yet the nmi occurs. its like it decided there is nothing to update and waites another frame.
so i am thinking either something is wrong and the nmi code should always update something and its not.
or i am not handling the ppu address and ppu address latch correctly. like the nmi code infact has nothing to update, and it expects the last ppu address ( or latch) to be correct (or the same as the last frame). should the ppu address latch be the same each frame if cpu never writes to a ppu register ?
i would also like to suggest a test if someone has the time or interest. test the ppu address for incrementing while writing to the registers, and while the ppu is rendering. are the same latches used for the registers as while rendering. (hope i explained that well) i have one ppu address and one ppu address latch that is used by both teh registers and the ppu
thanks
matt
i have checked nmi's and those are every frame, nothing that looks wrong.
i think i might have the ppu address and ppu address latch wrong. usually the code before every frame while in the town is writing to the ppu and setting the ppu address. on the frames with glitches it does nothing, yet the nmi occurs. its like it decided there is nothing to update and waites another frame.
so i am thinking either something is wrong and the nmi code should always update something and its not.
or i am not handling the ppu address and ppu address latch correctly. like the nmi code infact has nothing to update, and it expects the last ppu address ( or latch) to be correct (or the same as the last frame). should the ppu address latch be the same each frame if cpu never writes to a ppu register ?
i would also like to suggest a test if someone has the time or interest. test the ppu address for incrementing while writing to the registers, and while the ppu is rendering. are the same latches used for the registers as while rendering. (hope i explained that well) i have one ppu address and one ppu address latch that is used by both teh registers and the ppu
thanks
matt