To my knowledge, the 'delay 1 instruction' thing is only because the NMI flag changes on the last cycle of the STA/STX, which means the CPU has already started pipelining the following instruction. IE it's too late to do an interrupt because the next instruction has already started, therefore the NMI happens after the following instruction.
In that same vein, even if you could "cancel" the upcoming NMI by clearing $2000.7 (which I'm not sure you can do anyway), The 'cancel' would have the same 1-instruction delay because the $2000 write would occur on the last cycle of the STA/STX, which means the CPU has already started processing the interrupt by the time the write is performed.
The same phenomenon appears with tight CLI/SEI combos because those change the I flag on their last cycle
Code:
NOP
NOP
SEI
CLI
; <-- IRQ will never occur here
SEI
; <-- IRQ may occur here
CLI
; <-- IRQ will never occur here
NOP
; <-- IRQ may occur here
NOP
edit:
Just to clarify. In your original example... the NMI would happen after the
second $2000 write (not the first one)