Well, I've been trying to debug my cpu with nestest but I guess my CPU emulation is so buggy I can't even get nestest to work... So I have to keep looking in a log for what's wrong
Now I've kinda hit a wall and I can't find why nestest.nes tries to access the SRAM? Was I supposed to load the SRAM portion with something? Nestest tries to access $6056 which has the RTS instruction according to FCEU's log. But on my Emulator the value at that address is zero so it causes a BRK and therefore halts everything
FCEU's log:
My Log:
P register also seems off but that's another issue I guess
EDIT: Now I'm starting to think it might have something to do with the 'undefined' opcodes. I haven't really bothered to implement them yet. But I thought I wouldn't really need them?
Now I've kinda hit a wall and I can't find why nestest.nes tries to access the SRAM? Was I supposed to load the SRAM portion with something? Nestest tries to access $6056 which has the RTS instruction according to FCEU's log. But on my Emulator the value at that address is zero so it causes a BRK and therefore halts everything
FCEU's log:
Code:
$AB85:60 RTS A:36 X:FF Y:A9 P:nVUBdIZC
$6056:60 RTS A:36 X:FF Y:A9 P:nVUBdIZC
$FF01:00 BRK A:36 X:FF Y:A9 P:nVUBdIZC
$C5F4:40 RTI A:36 X:FF Y:A9 P:nVUBdIZC
$FF03:63 UNDEFINED A:36 X:FF Y:A9 P:nVUBdIZC
$FF05:3B UNDEFINED A:19 X:FF Y:A9 P:nvUBdIzC
$FF08:00 BRK A:19 X:FF Y:A9 P:nvUBdIzC
$C5F4:40 RTI A:19 X:FF Y:A9 P:nvUBdIzC
$6056:60 RTS A:36 X:FF Y:A9 P:nVUBdIZC
$FF01:00 BRK A:36 X:FF Y:A9 P:nVUBdIZC
$C5F4:40 RTI A:36 X:FF Y:A9 P:nVUBdIZC
$FF03:63 UNDEFINED A:36 X:FF Y:A9 P:nVUBdIZC
$FF05:3B UNDEFINED A:19 X:FF Y:A9 P:nvUBdIzC
$FF08:00 BRK A:19 X:FF Y:A9 P:nvUBdIzC
$C5F4:40 RTI A:19 X:FF Y:A9 P:nvUBdIzC
My Log:
Code:
AB85: 60 RTS A=37 X=FF Y=A9 P=01000101
6056: 0 BRK A=37 X=FF Y=A9 P=01000101
06C5: 0 BRK A=37 X=FF Y=A9 P=01000101
06C5: 0 BRK A=37 X=FF Y=A9 P=01000101
06C5: 0 BRK A=37 X=FF Y=A9 P=01000101
06C5: 0 BRK A=37 X=FF Y=A9 P=01000101
06C5: 0 BRK A=37 X=FF Y=A9 P=01000101
06C5: 0 BRK A=37 X=FF Y=A9 P=01000101
06C5: 0 BRK A=37 X=FF Y=A9 P=01000101
06C5: 0 BRK A=37 X=FF Y=A9 P=01000101
6056: 0 BRK A=37 X=FF Y=A9 P=01000101
06C5: 0 BRK A=37 X=FF Y=A9 P=01000101
06C5: 0 BRK A=37 X=FF Y=A9 P=01000101
06C5: 0 BRK A=37 X=FF Y=A9 P=01000101
06C5: 0 BRK A=37 X=FF Y=A9 P=01000101
06C5: 0 BRK A=37 X=FF Y=A9 P=01000101
06C5: 0 BRK A=37 X=FF Y=A9 P=01000101
06C5: 0 BRK A=37 X=FF Y=A9 P=01000101
06C5: 0 BRK A=37 X=FF Y=A9 P=01000101
P register also seems off but that's another issue I guess
EDIT: Now I'm starting to think it might have something to do with the 'undefined' opcodes. I haven't really bothered to implement them yet. But I thought I wouldn't really need them?