In 4-screen mirroring I understand that I should disallow writes to the MMC3 mirroring register, and that I'm not supposed to re-route the name/attr table address lines like you do for horizontal/vert mirroring. And I understand that 4-screen mirroring is not really any mirroring at all - you just actually have 4 physical 1KB slots.
I already know at least one way that I could implement 4SM with no problems, however, I want my implementation to be as accurate as possible. My method would be:
1) Add an extra 2KB of RAM to my board
2) My current 2KB of on-board console name/attr RAM is chip-selected by PPU A13 (as it was in the original NES). And that memory has an 11-bit address interface A10 through A0.
3) I would switch between the two 2KB chips using PPU A11. That is, A11=0 would select the original on-board 2KB name/attr RAM chip and A11=1 would select the on-cart 2KB RAM chip.
The above is easy for me to do with my FPGA. But....
My concern here is that I don't understand how (in the original NES) the in-console name/attr memory was _not_ read/written when the carts extra 2KB name/attr memory was read/written. For example, in the original NES the name/attr mem was chip-enabled by simple looking for PPU A13 to be asserted (which decoded that region of PPU memory). So, ignoring mirrored regions, this would decode _everything_ from $2000-$2FFF. And of course the PPU write line was attached to the internal name/attr mem as well.
So my question is, when I'm playing a 4SM game, and it goes and writes to its extra 2KB of name/attr RAM (e.g. $2800), how does it _not_ also write to (and thereby corrupt) the in-console name/attr mem (e.g. $2000)?? There is no way to tell the NES not to select the internal name/attr mem since it is automatically enabled by PPU A13.
Thanks!
Jonathon
Gauntlet used a 8K RAM chip as nametable memory. 4k went unused.
My understanding is that there are enough pins going to the cartridge that it can affect anything it wants to. For instance, mirroring is selected by how the pins go through the cartridge, then feed back into the NES where it selects which address lines go to the internal RAM. You could just as easily map cartridge ROM or RAM to the nametable memory.
Ya know there's a VRAM /CE pin? Four screen RAM is decoded with /A13, that's it.
That is, the /CS for the NES internal VRAM is exposed on the cartridge bus, and it's the cartridge's job to drive it, or just keep it deasserted to disable internal VRAM entirely.
blargg wrote:
That is, the /CS for the NES internal VRAM is exposed on the cartridge bus, and it's the cartridge's job to drive it, or just keep it deasserted to disable internal VRAM entirely.
Awesome! That's what I was looking for. I thought that's what kyuusaku was saying but I was hoping someone else would chime in to confirm. Thanks Blargg and kyuusaku.
Dwedit wrote:
Gauntlet used a 8K RAM chip as nametable memory. 4k went unused.
This was confusing me a bit until I figured out Dwedit actually meant Gauntlet II. Gauntlet only had an additional 2KB of VRAM in addition to the onboard 2KB.
GI :
http://bootgod.dyndns.org:7777/profile.php?id=473
GII:
http://bootgod.dyndns.org:7777/profile.php?id=103
But regardless, given how expensive SRAM was back in that day it is incredible to me that the company would spend so much money on an SRAM chip and then only use half of it. Crazy.
jwdonal wrote:
given how expensive SRAM was back in that day it is incredible to me that the company would spend so much money on an SRAM chip and then only use half of it. Crazy.
It probably had something to do with weighing the price of the SRAM against the price of the decoder circuitry.
If fact there is 8k on board + 2k in the NES, so 10k in total and only 4k of it is used, so 6k is wasted.
I guess the price of an 74HC00 + a 2k RAM was higher than the price of a 8k RAM alone... ?
May have also been an issue with PCB space. Since 8KB and 4KB SRAMs would have been the same size:
74 series + 4KB SRAM
occupies more area than
nothing + 8KB SRAM
And the cost of RAM isn't merely a function of the number of bits. There's fixed overhead per chip, and of course market volume; if 8K was used more than 2K, then it might be cheaper or available in the quantities needed. I mean, could you say that games with 8K WRAM should have used 2K WRAM, because their save games didn't need all the space? Well, actually Startropics did that, with the MMC6, and I've noticed that early SNES games with battery RAM also used 2K RAM chips as well...
Disclaimer: In this post I am specifically referring to a 4-screen mirroring game which has an additional 2KB of in-cart VRAM. One (only?) example of a game that does this is Gauntlet. I also disregard mirrored regions - but I am aware of them.
So I'm working on trying to get 4-screen mirroring working for my MMC3 mapper. I was hoping one of you could provide a bit more clarification on how it's supposed to work. I understand how the cart drives/controls the NES' 2KB internal CIRAM chip-enable signal in order to prevent write corruption (as explained above). That solves the problem for writes.
But how does the NES internally select which data bus to use during _reads_ by the PPU? For example, for a read from $2000-$27FF the PPU should receive data from the NES' internal CIRAM chip. And on a read from $2800-$2FFF the PPU should receive data from the cart's 2KB VRAM chip. But how does the NES physically select between the 2 busses (i.e. in hardware)?
From looking at the 72-pin cartridge pinout the only signal I can see that it would use would (again) be the CIRAM chip-enable line. So I'm thinking that whenever the cart disables the NES' internal CIRAM the NES motherboard switches to receiving data from the cart's PPU data bus instead. Is it just that simple? Haha, or am I totally confused?
They're on the same bus, there's no switching needed. It's just a matter of enabling the chips at the right time, which is what the CIRAM pins do.
so does that mean "chip-enable" in this case is synonymous with "output-enable"? Because you can't have 2 chips driving the same bus.
I draw the distinction between a "chip enable" and an "output enable" by whether or not the signal must be asserted for a write.
If the part's datasheet states that the rule is
- If /CE1=0 and /CE2=0 and /W=0, write
- If /CE1=0 and /CE2=0 and /W=1, read
then /CE1 and /CE2 are chip enables.
But if the rule is
- If /CE1=0 and /W=0, write
- If /CE1=0 and /CE2=0 and /W=1, read
then /CE1 is a chip enable and /CE2 is an output enable (also called /OE or /RD).
Agreed. So I'm thinking that the CIRAM /CE pin must actually be an "output-enable". Otherwise you would get bus contention on every read from the name/attr region of memory. This is what was confusing me. I should open up my NES and see if I can find the datasheet for the CIRAM SRAM chip and look at how the chip works with regards to driving its data bus.
Aha!! I found the datasheet for the NES' CIRAM SRAM chip. The chip actually has CE, OE, and WE inputs, _but_ whenever chip-enable (CE) is deasserted the other 2 inputs are "don't cares" and the chip's data bus is tri-stated. Sweet. Riddle solved.
Dwedit wrote:
Gauntlet used a 8K RAM chip as nametable memory. 4k went unused.
Note that it was clarified that Dwedit was actually talking about Gauntlet II since Gauntlet only has a 2KB SRAM chip.
I have some concerns regarding Dwedit's statement. According to Disch's mapper doc Gauntlet II doesn't use 4-screen mirroring at all. Also, bootgod's NesCartDB database says that it has 8KB of WRAM - _not_ VRAM.
So I'm confused, does Gauntlet II use 4-screen mirroring or not?
Gauntlet 2 appears to use Vertical mirroring.
I don't remember exactly where I read that they used half of an 8K chip in Gauntlet 1...
Hmmm....I have an idea. Could it be that you actually meant Rad Racer II??
Rad Racer II has an 8KB SRAM chip but only uses 4KB of it. This is verified in the NesCartDB as well:
http://bootgod.dyndns.org:7777/profile.php?id=137