Quote:
"Personally, I'd use "divider" to specify things that maintained an almost-50% duty cycle
I
absolutely agree with that. This actually messed my APU up for quite some time until I found the expected operation of the APU's divider
here. I am an HDL designer in my full-time job and in my experience the term "clock divider" has always meant what you describe.
I think a much better terminology for the APU clock "divider" would be a "clock-enable generator", which is a much more accurate description of its purpose. But of course, going and changing all that on the Wiki and in Blargg's apu_ref.txt is probably not worth the effort. :-/
But at least it's now documented HERE.