I have been working on more emulator accuracy the past few days and asking questions on 6502.org. I got pointed to the Visual6502 simulator which I'd looked at plenty of times in the past month or so, but didn't *really* look at it until just now.
The test ROM I'm currently working on is blargg's cpu_interrupts set. Using the expert mode of Visual6502 I created a test program and found something *very* interesting:
http://visual6502.org/JSSim/expert.html ... re=nmi,irq
The program being executed isn't much (NOPs)...but if you look at CPU cycle 9 (leftmost column) you'll see an NMI being triggered during the vector fetch phase of an IRQ sequence. If you then search down you'll notice something I found very *odd*. There's no NMI...ever.
Implementing a quick "hmm...what if I just don't check for NMI if I'm in my BRK routine and already at those fetch cycles" check made the test ROM pass.
You can easily vary the location of the NMI by changing the "&nmi0=nn&nmi1=mm" segment of the URL above. NMI is not recognized unless it is low in the first phase (first row) of a CPU clock cycle.
SO the question I have from all of this is...is there any documentation of the length of the PPU's NMI pulse?
This link shows an NMI that is long enough to be vectored to after the INX of the IRQ.
http://visual6502.org/JSSim/expert.html ... re=nmi,irq
Utterly fascinating!
The test ROM I'm currently working on is blargg's cpu_interrupts set. Using the expert mode of Visual6502 I created a test program and found something *very* interesting:
http://visual6502.org/JSSim/expert.html ... re=nmi,irq
The program being executed isn't much (NOPs)...but if you look at CPU cycle 9 (leftmost column) you'll see an NMI being triggered during the vector fetch phase of an IRQ sequence. If you then search down you'll notice something I found very *odd*. There's no NMI...ever.
Implementing a quick "hmm...what if I just don't check for NMI if I'm in my BRK routine and already at those fetch cycles" check made the test ROM pass.
You can easily vary the location of the NMI by changing the "&nmi0=nn&nmi1=mm" segment of the URL above. NMI is not recognized unless it is low in the first phase (first row) of a CPU clock cycle.
SO the question I have from all of this is...is there any documentation of the length of the PPU's NMI pulse?
This link shows an NMI that is long enough to be vectored to after the INX of the IRQ.
http://visual6502.org/JSSim/expert.html ... re=nmi,irq
Utterly fascinating!