Firstly, what is the speed of the Sega Genesis's RAM, and how does the DMA access it at 3.36 mhz if the 68000 accesses it at 1.92 mhz?
Secondly, if the SNES's cpu goes from a 8 master cycle RAM access to a 6 master cycle ROM access, and back to an 8 master cycle RAM access, doesn't that cause the CPU to be 2 master cycles out of sync with the RAM?, and why does it still work?
Here's how I understand part of the answer to your first question: In the Mac Plus, Atari ST, and Amiga, the video hardware and the CPU ordinarily take turns accessing RAM. Depending on the video mode, the CPU may get more or fewer time slots. When the CPU wants to access RAM, it asserts a request signal, and once the bus is ready, the memory controller acknowledges the request. The 68000 has a lot of internal operation cycles for every instruction, comparable to the Z80 and far more than the 6502 family.
Here's how I understand the answer to your second question: The Super NES CPU contains a 65816 CPU and a memory controller circuit. The memory controller divides the 21.5 MHz master clock by 6 to 8* depending on the address to produce a clock signal going into the 65816, which fluctuates between 2.7 MHz (RAM and slow ROM) and 3.6 MHz (fast ROM and internal operation). This is not unlike how the front-end of an NES CPU divides the master clock by 12 to make the 6502's clock.
* The two controller I/O ports are even slower.
Neither of the two questions you've answered correctly.
Let me put this another way:
Lets say you have a RAM chip running at exactly 10 Mhz
Lets say you have a CPU chip running at exactly 9 Mhz
Would this work? Or will the two chips misread eachother?
I think what he's trying to explain is in between the chip not using it the other uses the RAM if it's ready. It'll wait if it's not available.
I thought the 68000 is halted during DMA?
I was asking what happens when the CPU clock is out of sync with the RAM clock.
psycopathicteen wrote:
I thought the 68000 is halted during DMA?
And I thought the way this halting was done was by using the acknowledge signal.
Quote:
I was asking what happens when the CPU clock is out of sync with the RAM clock.
"RAM clock"? As I understand it, most RAMs of that period (1989) use asynchronous interfaces, such that the RAM slows down to match the speed of whatever is accessing it at the moment. That's why 70 ns SRAMs still work with a much slower 1.79 MHz 6502.
tepples wrote:
"RAM clock"? As I understand it, most RAMs of that period (1989) use asynchronous interfaces, such that the RAM slows down to match the speed of whatever is accessing it at the moment. That's why 70 ns SRAMs still work with a much slower 1.79 MHz 6502.
Thanks, this answers both of my original questions.