This is my first try to use CPLD
I don't want to burn anything so I want to ask before continuing!
I didn't use any VHDL or Verilog language!
I just made the Schematic in Xilinx ISE 14.2 and then produced the jed file with :
Process --> Implement to Module
Is it OK to continue with programming the jed file?
I am going to program XC9572-7-PC44 by using iMPACT and this programmer (NFP102)
Also I want to know how many times I can erase and flash this CPLD (XC9572)?
Thanks in advance
I don't want to burn anything so I want to ask before continuing!
I didn't use any VHDL or Verilog language!
I just made the Schematic in Xilinx ISE 14.2 and then produced the jed file with :
Process --> Implement to Module
Is it OK to continue with programming the jed file?
I am going to program XC9572-7-PC44 by using iMPACT and this programmer (NFP102)
Also I want to know how many times I can erase and flash this CPLD (XC9572)?
Thanks in advance