I am trying to understand how MMC3 controls WRAM.
Please correct me if any info is wrong :
Some cartridges have RAM at $6000-$7FFF, which may or may not be battery-backed.
Usually a regular 8KB SRAM like KM6264 is used.
KM6264 has four control pins :
/WE (pin27) --> MMC3 pin42 : When it is high cpu can read SRAM, when it is low cpu can write SRAM. 6th bit of $A001 [0:W 1:R] controls this pin.
+CE (pin26) --> MMC3 pin41 : When it is high SRAM is enabled, when it is low SRAM is disabled. 7th bit of $A001 [0:Dis 1:En] controls this pin.
/OE (pin22) --> GND : When it is high SRAM disables its output, when it is low SRAM gives output. This pin is tied to GND so it gives output all the time.
/CE (pin20) --> MMC3 pin30 : When cpu access (read or write) $6000 ~ $7FFF this pin goes low to enable SRAM, otherwise it stay high to prevent bus conflict
I want to use AX5202P (MMC3 Clone)
As I tested AX5202P, it won't respond to STA $A001 at all
It seems that its WRAM /WE is just outputting 5V
And its WRAM +CE is just outputting GND
But its WRAM /CE works just fine (because it responds to STA $6800)
So I am either missing something about WRAM /WE and +CE or AX5202P doesn't have $A001 register at all.
Is my schematic correct about WRAM control pins? So that I can add WRAM /WE and +CE to AX5202P in the future.
Can anyone test my simple nes file on a real MMC3 to see if its WRAM /WE and WRAM +CE respond to STA $A001?
WRAM /WE (or +CE) -- LDE -- GND
Thanks in advance
Please correct me if any info is wrong :
Some cartridges have RAM at $6000-$7FFF, which may or may not be battery-backed.
Usually a regular 8KB SRAM like KM6264 is used.
KM6264 has four control pins :
/WE (pin27) --> MMC3 pin42 : When it is high cpu can read SRAM, when it is low cpu can write SRAM. 6th bit of $A001 [0:W 1:R] controls this pin.
+CE (pin26) --> MMC3 pin41 : When it is high SRAM is enabled, when it is low SRAM is disabled. 7th bit of $A001 [0:Dis 1:En] controls this pin.
/OE (pin22) --> GND : When it is high SRAM disables its output, when it is low SRAM gives output. This pin is tied to GND so it gives output all the time.
/CE (pin20) --> MMC3 pin30 : When cpu access (read or write) $6000 ~ $7FFF this pin goes low to enable SRAM, otherwise it stay high to prevent bus conflict
I want to use AX5202P (MMC3 Clone)
As I tested AX5202P, it won't respond to STA $A001 at all
It seems that its WRAM /WE is just outputting 5V
And its WRAM +CE is just outputting GND
But its WRAM /CE works just fine (because it responds to STA $6800)
So I am either missing something about WRAM /WE and +CE or AX5202P doesn't have $A001 register at all.
Is my schematic correct about WRAM control pins? So that I can add WRAM /WE and +CE to AX5202P in the future.
Can anyone test my simple nes file on a real MMC3 to see if its WRAM /WE and WRAM +CE respond to STA $A001?
WRAM /WE (or +CE) -- LDE -- GND
Thanks in advance