I'm writing a PowerPak mapper (an experimental one with a coprocessor) that requires me to map the FPGA's block RAM into the CPU's address space, probably at $5xxx.
I'm using Loopy's mapper source as a reference, and it looks like the part that actually routes PRG ROM and WRAM to the NES's CPU is the Game Genie module, which I'm disabling because I won't have spare logic for it (coprocessor uses 75% when synthesized as a top level module). Do I just set nesprgdout to ramprgdin unless the address space is inside $5xxx?
For accessing the block RAM itself I tried this, making six dual ported block RAM primitives and using a multiplexer to choose the appropriate output from one of them. The problem with that is it uses like 9% of the FPGA space. Is there a way to do this with less resources? Are the space usage counts when marking each different module as the top level one even accurate? I made a module with both this block RAM and the coprocessor together and it added less than 9% to the coprocessor's usage amount.
I'm using Loopy's mapper source as a reference, and it looks like the part that actually routes PRG ROM and WRAM to the NES's CPU is the Game Genie module, which I'm disabling because I won't have spare logic for it (coprocessor uses 75% when synthesized as a top level module). Do I just set nesprgdout to ramprgdin unless the address space is inside $5xxx?
For accessing the block RAM itself I tried this, making six dual ported block RAM primitives and using a multiplexer to choose the appropriate output from one of them. The problem with that is it uses like 9% of the FPGA space. Is there a way to do this with less resources? Are the space usage counts when marking each different module as the top level one even accurate? I made a module with both this block RAM and the coprocessor together and it added less than 9% to the coprocessor's usage amount.