The UMC UA6527 & UA6527P(al) seem to be fairly common chips and function very well as a 2A03 CPU clone, except for the reversed duty cycles. I understand that when a NES game wants a 50% duty cycle pulse, it writes 10xxxxxx (x=don't care) to either $4000 or $4004. Similarly, if it wants a 12.5% duty cycle pulse, it writes 00xxxxxx to the register. (I hope I don't have my endianness screwed up here). The other two options, 25% and 75%, sound the same and can be written with a 01 or 11 to the high bits of $4000 or $4004.
It seems to me that if you have a discrete chip, you can fix this using extra logic either on a custom PCB or a daughterboard that wedges in between the CPU and the socket. My idea is that when $4000 or $4004 is asserted on the address bus, the high bit of the data write is inverted. As you can see from above, only the highest bit is important here. Flipping that bit restores the agreement between what the game wants and the substitute APU wants for the identical pulse wave.
My idea is to use a pair of 74'688 8-bit comparators, a 74'08 AND gate to tie the outputs of the comparators together and finally a 74'2266 XNOR gate to ensure the bit is flipped only when the comparators are active and otherwise left untouched. The address bus is 16-bit and has to be passed through to the CPU, but bit 3 would not be connected to the comparators to allow for $4000 or $4004.
The P=Q outputs, active low, go into the AND to ensure that a 0 is output only when both outputs are low. That 0 is fed into one input of an XNOR gate and the data bit (7) is the other input. When the comparators do not equal 4000 or 4004, then their input will be a 1 and the data bit is sent through the gate the same way it entered. If the comparators equal 4000 or 4004, then the data bit will end up being the opposite of the way it came in.
I'm sure someone with more experience in digital logic design could propose a more efficient way to accomplish this task. Is my idea sound or dumb?
It seems to me that if you have a discrete chip, you can fix this using extra logic either on a custom PCB or a daughterboard that wedges in between the CPU and the socket. My idea is that when $4000 or $4004 is asserted on the address bus, the high bit of the data write is inverted. As you can see from above, only the highest bit is important here. Flipping that bit restores the agreement between what the game wants and the substitute APU wants for the identical pulse wave.
My idea is to use a pair of 74'688 8-bit comparators, a 74'08 AND gate to tie the outputs of the comparators together and finally a 74'2266 XNOR gate to ensure the bit is flipped only when the comparators are active and otherwise left untouched. The address bus is 16-bit and has to be passed through to the CPU, but bit 3 would not be connected to the comparators to allow for $4000 or $4004.
The P=Q outputs, active low, go into the AND to ensure that a 0 is output only when both outputs are low. That 0 is fed into one input of an XNOR gate and the data bit (7) is the other input. When the comparators do not equal 4000 or 4004, then their input will be a 1 and the data bit is sent through the gate the same way it entered. If the comparators equal 4000 or 4004, then the data bit will end up being the opposite of the way it came in.
I'm sure someone with more experience in digital logic design could propose a more efficient way to accomplish this task. Is my idea sound or dumb?