supercat wrote:
I'm not sure why inverted M2
A lot of 74 parts use an active-low enable.
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or inverted R/W
Obviates the need for bus conflict prevention.
The NES already has a 74HCU04 to generate the clock for the CIC, and the other five are enlisted in CIC clock distribution (to prevent the cartridge for being able to short out the CIC clock), PPU /A13 generation, audio amplifier, and LED driver. I'm pretty certain that at least one inverter could be repurposed without compromising those functions.
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BTW, I'm curious how the PPU memory layout evolved, since it seems needlessly complex from both a hardware and software standpoint.
Are you already familiar with the TMS9918? (MSX, SG1000). Beyond things like raster timing, its memory layout also influenced the NES PPU.... oh you're talking specifically about the attribute table.
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16x8, 8x16, or ignore-attributes modes
Non-square attribute zones would probably have been deemed too much of a pain to use - at least, that's what I heard when people more skilled with pixel art were told that we could give them finer attribute zones. No-attribute mode probably would have been nixed for being insufficiently colorful.
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could have accommodated games that need double buffering.
I can guarantee that they never even considered double buffering as a use case. I'm comfortable saying that porting all of Nintendo's existing arcade games, as of 1983, was a design parameter for the PPU, and that includes smooth scrolling (e.g. Sky Skipper). But double buffering in 1983 was just too expensive for something where other options look good enough.
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I wonder if the intention was to make the chip usable with a pair of 1Kx4 static RAMs?
They clearly bent over backwards to fit into 1KiB, but I'm a little skeptical that they ever specifically aimed at having
only 1KiB of RAM for the PPU.