I got Gimmick 2 hack which was done using INL-XO-ROM PCB. My version does not have expansion sound, but the PCB at first glance looks like super-dooper:
* place for PRG1-ROM (up to 8MB), PRG2-ROM (up to 512 kB) - was PRG1 meant to be for storing games and PRG2 for firmware when using micro sd card?),
* place for CHR-ROM (up to 512 kB),
* place for PRG/CHR-RAM (even up to 128kB),
* place for battery,
* place for AY-3-8910,
* place for micro sd card,
* some other stuff (logic to support MMC2/MMC4) and a few unpopulated chips.
Probably one universal board for many applications.
Luckily I have a lot of AY-3-8910 chips so I reverse engineered the board mainly because I was curious which components need to be soldered to make audio expansion work.
* The board is build using LAMXO256 CPLD. Does not seem to be very popular, nor cheap (2$) but with similar capacity (256 LUT) and I/Os (78) versus Altera EPM240 (1$, 240 macrocells, 80 IO pins)
* 16 channel 74LVC16245 buffers used for 3V3-5V translation (4$) - I prefer 8 channel 74LVC245 (0.1$), smaller and easier to route signals. And they still ran out of the pins and needed to translate PPU-A13/PPU-A12 using resistor divider
* CON1: There is place for micro SD - loading games like in everdrive?
* IC10: There is place for SPI memory (probably for Dragon Ball and other games that require SPI flash for storing savestates)
* IC9 (STM32F0, unpopulated) / IC13 (STMSTM8S003F3P6) - seems to be responsible for CIC stun. It also has access to micro SD card pins and audio output - was this meant to be used to play back music from sd card and output it to NES?
* Programming CPLD done via EXP0 (TDO) / EXP1 (TDI) / EXP2 (TMS) / EXP3 (TCK) headers
* There is a jumper which selects if WRAM-A12 is tied to CPU-A12 or driven by CPLD (PRG-ROM-A12 is driven by the same pin) - 4kB banking support, woah, can be used to play NSF
* JP3 - unpopulated 5 pin small connector (was it for external audio hook-up?)
Flaws:
* The right terminal of battery (negative) is not routed to anything,
* One of the chasis pins of micro sd card is not routed to anything,
* One leg of R4 is not routed to anything,
* CPLD directly sees PPU A10-A13, but for MMC2/MMC4 it also needs to check if PPU A3-A9 are all ones (and so they used NAND - clever, I did similar trick but using diodes). Weird thing is that they do not care for PPU A0..A2 (according to wiki - MMC2 latch 0 responds only to one address)
* CPLD controls output enable of IC8 buffer and 1/2 of IC7 buffer using the same control line. For IC8 this is strange cause this buffer converts CPU address line which should be always enabled.
* place for PRG1-ROM (up to 8MB), PRG2-ROM (up to 512 kB) - was PRG1 meant to be for storing games and PRG2 for firmware when using micro sd card?),
* place for CHR-ROM (up to 512 kB),
* place for PRG/CHR-RAM (even up to 128kB),
* place for battery,
* place for AY-3-8910,
* place for micro sd card,
* some other stuff (logic to support MMC2/MMC4) and a few unpopulated chips.
Probably one universal board for many applications.
Luckily I have a lot of AY-3-8910 chips so I reverse engineered the board mainly because I was curious which components need to be soldered to make audio expansion work.
* The board is build using LAMXO256 CPLD. Does not seem to be very popular, nor cheap (2$) but with similar capacity (256 LUT) and I/Os (78) versus Altera EPM240 (1$, 240 macrocells, 80 IO pins)
* 16 channel 74LVC16245 buffers used for 3V3-5V translation (4$) - I prefer 8 channel 74LVC245 (0.1$), smaller and easier to route signals. And they still ran out of the pins and needed to translate PPU-A13/PPU-A12 using resistor divider
* CON1: There is place for micro SD - loading games like in everdrive?
* IC10: There is place for SPI memory (probably for Dragon Ball and other games that require SPI flash for storing savestates)
* IC9 (STM32F0, unpopulated) / IC13 (STMSTM8S003F3P6) - seems to be responsible for CIC stun. It also has access to micro SD card pins and audio output - was this meant to be used to play back music from sd card and output it to NES?
* Programming CPLD done via EXP0 (TDO) / EXP1 (TDI) / EXP2 (TMS) / EXP3 (TCK) headers
* There is a jumper which selects if WRAM-A12 is tied to CPU-A12 or driven by CPLD (PRG-ROM-A12 is driven by the same pin) - 4kB banking support, woah, can be used to play NSF
* JP3 - unpopulated 5 pin small connector (was it for external audio hook-up?)
Flaws:
* The right terminal of battery (negative) is not routed to anything,
* One of the chasis pins of micro sd card is not routed to anything,
* One leg of R4 is not routed to anything,
* CPLD directly sees PPU A10-A13, but for MMC2/MMC4 it also needs to check if PPU A3-A9 are all ones (and so they used NAND - clever, I did similar trick but using diodes). Weird thing is that they do not care for PPU A0..A2 (according to wiki - MMC2 latch 0 responds only to one address)
* CPLD controls output enable of IC8 buffer and 1/2 of IC7 buffer using the same control line. For IC8 this is strange cause this buffer converts CPU address line which should be always enabled.