A couple nights ago, I took a couple hours to sketch out a design for a mapper using a 74HC670 and a few combinational chips. Features include three switchable 8 KiB banks and one switchable 4 KiB bank, allowing use of DPCM. It can be put together with four chips (plus PRG ROM, CHR RAM, and lockout defeat) for a 128 KiB PRG capacity or six chips (plus PRG ROM, CHR RAM, and lockout defeat) for a 2 MiB PRG capacity.
Memory map
$4018-$7FFF: Handled by other logic
$8000-$9FFF: Switchable bank 0
$A000-$BFFF: Switchable bank 1
$C000-$DFFF: Switchable bank 2
$E000-$EFFF: Switchable bank 3
$F000-$FFFF: Fixed bank
Register interface
Registers at $8000, $A000, $C000: Bank select
Register at $E000: Bank select
Parts summary
PRG ROM (128 KiB)
CHR RAM (8 KiB)
Lockout defeater
74HC670: register file
74HC08 Quad 2-input AND: Compute MapperWrite and FixedF000
74HC32 Quad 2-input OR: Apply FixedF000
74HC02 Quad 2-input NAND: Compute PRG ROM /OE
Optional:
Additional 670 and 32 to allow PRG up to 2 MiB
Combinational logic signals
MapperWrite = R/W AND CPU /A15
Determines when the CPU is writing to the mapper.
FixedF000 = (A14 AND A13) AND A12
Determines when the CPU is trying to access the fixed 4 KB bank.
PRG ROM A16-A13 = Q3-Q0 OR FixedF000
PRG ROM /OE is computed as in ANROM.
Use of 670
74HC670 is a 4-entry 4-bit register file. It has the following pins:
Power VCC, GND
Write address WB-WA
Write data D3-D0
Write enable /WE
Read address RB-RA
Read value Q3-Q0
Read enable /RE
In this mapper they are assigned thus:
D3-D0 = CPU D3-D0
RB-RA, WB-WA = CPU A14-A13
/RE = 1
Q3-Q0 to PRG ROM A16-A13
/WE = MapperWrite
So is this viable?
Memory map
$4018-$7FFF: Handled by other logic
$8000-$9FFF: Switchable bank 0
$A000-$BFFF: Switchable bank 1
$C000-$DFFF: Switchable bank 2
$E000-$EFFF: Switchable bank 3
$F000-$FFFF: Fixed bank
Register interface
Registers at $8000, $A000, $C000: Bank select
Code:
7654 3210
||||
++++- Select 8 KB bank
||||
++++- Select 8 KB bank
Register at $E000: Bank select
Code:
7654 3210
||||
++++- Select 8 KB bank whose first half is mapped
||||
++++- Select 8 KB bank whose first half is mapped
Parts summary
PRG ROM (128 KiB)
CHR RAM (8 KiB)
Lockout defeater
74HC670: register file
74HC08 Quad 2-input AND: Compute MapperWrite and FixedF000
74HC32 Quad 2-input OR: Apply FixedF000
74HC02 Quad 2-input NAND: Compute PRG ROM /OE
Optional:
Additional 670 and 32 to allow PRG up to 2 MiB
Combinational logic signals
MapperWrite = R/W AND CPU /A15
Determines when the CPU is writing to the mapper.
FixedF000 = (A14 AND A13) AND A12
Determines when the CPU is trying to access the fixed 4 KB bank.
PRG ROM A16-A13 = Q3-Q0 OR FixedF000
PRG ROM /OE is computed as in ANROM.
Use of 670
74HC670 is a 4-entry 4-bit register file. It has the following pins:
Power VCC, GND
Write address WB-WA
Write data D3-D0
Write enable /WE
Read address RB-RA
Read value Q3-Q0
Read enable /RE
In this mapper they are assigned thus:
D3-D0 = CPU D3-D0
RB-RA, WB-WA = CPU A14-A13
/RE = 1
Q3-Q0 to PRG ROM A16-A13
/WE = MapperWrite
So is this viable?