It's a question that tortures me for a while.
What is present on the CPU bus, when the CPU rests (or does an internal operation wihtout any acess on the bus) ? CPUs with dual /RD and /WR lines (like the NES's PPU too) can just leave them both high for a cicle. However, CPUs with only one R/W line and a validation/clock like (PHI2) cannot do this.
For example when the 6502 exectutes a STA $xx (as a exemple) the sequence is the following :
1 - Fetch the opcode (the CPU bus reads at the programm counter location)
2 - Fetch the argument (the CPU bus reads at the programm counter location+1)
3 - Writes the accumulator to memors (the CPU bus writes to the adress specified by the argument read in 2).
So each step effectively takes an acess to the bus (the opcode is 3 cycles).
However, this don't work for all opcodes. Here you are a NOP sequence :
1 - Fetch the opcode (the CPU bus reads the NOP opcode)
2 - Do nothing (what is present on the CPU bus ??)
Or another example for ROL A :
1 - Fetch the opcode (the CPU reads the ROL A opcode)
2 - Rotate the acumulator (no acess to the CPU bus, what is present on it ?)
I can see only 2 solutions :
1 - The M2 lines stay low for one (or more) cycles.
2 - The CPU reads a dummy adress.
What is present on the CPU bus, when the CPU rests (or does an internal operation wihtout any acess on the bus) ? CPUs with dual /RD and /WR lines (like the NES's PPU too) can just leave them both high for a cicle. However, CPUs with only one R/W line and a validation/clock like (PHI2) cannot do this.
For example when the 6502 exectutes a STA $xx (as a exemple) the sequence is the following :
1 - Fetch the opcode (the CPU bus reads at the programm counter location)
2 - Fetch the argument (the CPU bus reads at the programm counter location+1)
3 - Writes the accumulator to memors (the CPU bus writes to the adress specified by the argument read in 2).
So each step effectively takes an acess to the bus (the opcode is 3 cycles).
However, this don't work for all opcodes. Here you are a NOP sequence :
1 - Fetch the opcode (the CPU bus reads the NOP opcode)
2 - Do nothing (what is present on the CPU bus ??)
Or another example for ROL A :
1 - Fetch the opcode (the CPU reads the ROL A opcode)
2 - Rotate the acumulator (no acess to the CPU bus, what is present on it ?)
I can see only 2 solutions :
1 - The M2 lines stay low for one (or more) cycles.
2 - The CPU reads a dummy adress.