The amount of time required for A12 to be low must be greater than 9 PPU cycles, because it has been observed that the counter doesn't count scanlines if both BG and sprite rendering use the upper pattern table. In this scenario, A12 will be low for nine consecutive cycles once per scanline (PPU cycles 336-340 at the end of a scanline + cycles 0-3 at the start of the following scanline).
Has anyone ever tested this on an actual MMC3?
Code:
STA $E000
BIT $2002
LDA #$00
STA $2006
STA $2006
LDA #$01
STA $C000
STA $C001
STA $E001
LDA #$10
STA $2006
STA $2006
LDA #$0F
STA $2006
LDA #$FF
STA $2006
LDA $2007
CLI
This code sets the IRQ reload count to 1 and resets the counter via $C001. It then performs one A12 clock by writing $1010 to $2006 (this reloads the counter, setting it to 1). It then writes $0FFF to $2006 and immediately reads from $2007, causing the address to increment to $1000. This will cause A12 to be low for about 4 CPU cycles, or around 12 PPU cycles (NTSC). If the MMC3 sees the change, the counter will decrement to zero and cause an IRQ. If the MMC3 doesn't see the change, the counter will be unaffected.