Bregalad wrote:
I don't know why you call any of it sneaky.
Tricky, because it doesn't have allow any setup times (so it's not suitable for slow memory or DRAM etc) and because of the /WE priority which is clever but isn't standard practice.
Bregalad wrote:
It's written on official 6264 datesheet that whenever /WE is low, the /OE is bypassed, as all pins are input anyway.
That's how SRAMs are wired on EVERY Nintendo made board that have them (all least every standard ones).
I understand that it works, but Nintendo doesn't always do it the "right" way, they do it the cheapest way such as bulk 74161 as 4-bit registers and the /ROMSEL signal which relies entirely on relatively fast asynchronous memory and doesn't let you recover A15 at Phi1.
Bregalad wrote:
And positive CE is also present on 128 KB SRAMs, but lacks in 32 KB and 2 KB SRAMs.
And practically all other SRAM, DRAM and PROM chips. Again it's not a "bad" thing, just not universally compatible.
Bregalad wrote:
And I don't know what you are talking about bus conflicts. As long RAM is only enabled for $6000-$7ffff, there cannot be any bus conflicts, since nothing else is mapped here.
I was talking about preventing $8000-FFFF conflicts at mapper writes, not SRAM ;)
Edit: After some brain crunching I found that only 5 NAND2s instead of 6 could be used to preform the logic I posted above and consequently that a single 7410 could be used too! It's only ~$0.10 more than 7400, ~$0.05 more than 7408 but it can properly decode any memory to $6000, and allow for setup times, and reconstruct /RD and /WR to remove mapper busconflicts: