1) If you were to map (e.g.) RAM in the CPU from $4000 to $5fff, clearly you'd get bus conflicts on reading the joysticks ($4016, $4017). But do you get a conflict on reading from internal registers (e.g. $4015)? On a write to $4000 to $4017, does the value appear on the data bus?
With RAM there it clearly doesn't matter if you write nonsense to the bottom 24 addresses, but ROM or other peripherals would be a different question.
2) So the NES uses a 74'139 to produce the select signals for the WRAM and the PPU. They use one of the two selectors to decode /(A15&PH2) (clearly forwarded to the cartridge) and /(/A15&PH2), and the other takes that (as the enable) and A14 and A13 to generate the /CS for the WRAM and the PPU. (thus enabling them to not need a separate 4-NAND for the WRAM /CS)
So the point is, how does having the /(A15&PH2) signal on the cartridge simplify the decoing logic there? (Otherwise they could have used a 74'138 and allocated less addressable space to each of the WRAM and PPU)
2.5) Any ideas on why they put A15 and D0-D7 on the expansion port, but nothing else directly useful? It seems likely that the inputs to the 74'368s and outputs from the $4016 latch are there to allow you to use famicom peripherals on the NES, given the right converter.
3) It would be a fairly simple piece of logic to allow more than 4 screens (the $2000-$2fff stuff in the PPU) -- just detect the single cycle gap (on pixel 341) and adjust one of the PPU address lines with a signal that goes from 0 to 1 on name table fetches when it starts fetching name table from the left page after fetching from the right page on the same scanline. Because the PPU fetches the two leftmost background blocks during the previous scanline, this would work badly with copper effects -- but it would work on all scanlines because of the dummy fetches on scanline 20. Would this be at all useful?
Relatedly, has anyone ever made a hack (or real thing?) that uses the 2k VRAM as both name table and pattern table (to reduce part count)? With only 64 patterns, it wouldn't look very good, but it would be enough to, say, build a cart containing Escape from Pong.
With RAM there it clearly doesn't matter if you write nonsense to the bottom 24 addresses, but ROM or other peripherals would be a different question.
2) So the NES uses a 74'139 to produce the select signals for the WRAM and the PPU. They use one of the two selectors to decode /(A15&PH2) (clearly forwarded to the cartridge) and /(/A15&PH2), and the other takes that (as the enable) and A14 and A13 to generate the /CS for the WRAM and the PPU. (thus enabling them to not need a separate 4-NAND for the WRAM /CS)
So the point is, how does having the /(A15&PH2) signal on the cartridge simplify the decoing logic there? (Otherwise they could have used a 74'138 and allocated less addressable space to each of the WRAM and PPU)
2.5) Any ideas on why they put A15 and D0-D7 on the expansion port, but nothing else directly useful? It seems likely that the inputs to the 74'368s and outputs from the $4016 latch are there to allow you to use famicom peripherals on the NES, given the right converter.
3) It would be a fairly simple piece of logic to allow more than 4 screens (the $2000-$2fff stuff in the PPU) -- just detect the single cycle gap (on pixel 341) and adjust one of the PPU address lines with a signal that goes from 0 to 1 on name table fetches when it starts fetching name table from the left page after fetching from the right page on the same scanline. Because the PPU fetches the two leftmost background blocks during the previous scanline, this would work badly with copper effects -- but it would work on all scanlines because of the dummy fetches on scanline 20. Would this be at all useful?
Relatedly, has anyone ever made a hack (or real thing?) that uses the 2k VRAM as both name table and pattern table (to reduce part count)? With only 64 patterns, it wouldn't look very good, but it would be enough to, say, build a cart containing Escape from Pong.