Trying to get reacquainted with the PPU:
* I've been looking at the Famicom (ntd_8bit.jpg) schematics. It shows that PPU /CS (/DBE) is asserted during the high state of Phi-2. Does Phi-2 high indicate the address bus is valid? (maybe analogous to /MREQ on a Z80 or /AS on a 68000)
* A 2SA937 transistor is used to amplify the video output. This part isn't available anymore. What is a suitable replacement? The video output circuitry seems deceptively simple, assuming Nintendo skimped on quality for a lower part count are there any modifications that can be made for better composite video output other than what the schematic shows?
* To my understanding when the PPU is in "Slave" mode, it outputs data on the EXT3-0 pins corresponding to the 2-bit pixel and 2-bit attribute information for both sprites and backgrounds. However there is no way to tell if pixel data belongs to a sprite or the background.
If all palette entries for opaque sprite pixels were set to $30 (max luminance) and the remaining ones were set to $00 (min. luminance without getting into the sync range), the video output would then include a sprite-or-background indicator. I don't know the actual voltages but the video output could then be like this:
0V - ("Blacker than black") Sync
.3V - (Black) Opaque background pixel or transparent sprite pixel
1V - (White) Opaque sprite pixel
The output could be run into a LM1881 to extract the composite sync portion of the signal for driving a monitor , and from there you'd somehow strip the sync information out and coax the latter two to TTL compatible signals. Now you could differentiate between sprite and background pixels, and I guess run the output into something fancy like a RAMDAC or mix it with the digital output of another PPU, etc.
But are the EXT3-0 outputs in sync with the composite video output, or does it lead or lag it by any amount? Maybe it wouldn't be possible to latch EXT3-0 and the recreated sprite indicator bit at the same time? How feasible is this?
* I've been looking at the Famicom (ntd_8bit.jpg) schematics. It shows that PPU /CS (/DBE) is asserted during the high state of Phi-2. Does Phi-2 high indicate the address bus is valid? (maybe analogous to /MREQ on a Z80 or /AS on a 68000)
* A 2SA937 transistor is used to amplify the video output. This part isn't available anymore. What is a suitable replacement? The video output circuitry seems deceptively simple, assuming Nintendo skimped on quality for a lower part count are there any modifications that can be made for better composite video output other than what the schematic shows?
* To my understanding when the PPU is in "Slave" mode, it outputs data on the EXT3-0 pins corresponding to the 2-bit pixel and 2-bit attribute information for both sprites and backgrounds. However there is no way to tell if pixel data belongs to a sprite or the background.
If all palette entries for opaque sprite pixels were set to $30 (max luminance) and the remaining ones were set to $00 (min. luminance without getting into the sync range), the video output would then include a sprite-or-background indicator. I don't know the actual voltages but the video output could then be like this:
0V - ("Blacker than black") Sync
.3V - (Black) Opaque background pixel or transparent sprite pixel
1V - (White) Opaque sprite pixel
The output could be run into a LM1881 to extract the composite sync portion of the signal for driving a monitor , and from there you'd somehow strip the sync information out and coax the latter two to TTL compatible signals. Now you could differentiate between sprite and background pixels, and I guess run the output into something fancy like a RAMDAC or mix it with the digital output of another PPU, etc.
But are the EXT3-0 outputs in sync with the composite video output, or does it lead or lag it by any amount? Maybe it wouldn't be possible to latch EXT3-0 and the recreated sprite indicator bit at the same time? How feasible is this?