kevtris wrote:
If that were the case, half the mappers wouldn't work. MMC3 for example can map WRAM at 6000-7fff and registers all through 8000-ffff
I was only going off of the information I found on the Wiki,
on this page:
Quote:
Some gotchas to watch out for include the fact that PRG /CE and M2, used together to decode $6000-$7FFF, don't change at the same time. Writes to a mapper register at $E000-$FFFF can cause spurious writes to PRG RAM,
as pointed out by loopy.kevtris wrote:
Address and R/W are always valid when M2 is high (and a little while after M2 falls).
So yeah, the A lines would change before /CE changes, but this entire issue of concern is completely moot if M2 always clocks
after the A lines and /CE are stable. If this is the case, then this information needs to be corrected before others (like me) get the wrong idea.
Edit:
Also, if PRG /CE is the result of !(M2 * A15), then wouldn't PRG /CE always change
after M2 clocks, since the signal has to go through a logic gate before reaching the cart? In that case, you'll always have a split instant where, if you're accessing address E000 for example, 6000 will be on the A lines while M2 is high. Even though PRG /CE will change an instant later, which will give me an address of E000, the damage will be already (potentially) done if I was performing a write, because (write something at 6000) will be fed to the cart for one instant before the correct (write something at E000) is sent.
If this is the case, wouldn't my previous solution be a viable workaround, for discrete mappers?