So I started REing this board a couple days ago (as part of my "get everything in NesCartDB in the wiki" project), and ran into trouble because enough traces are hidden under ICs and there's no complete functional description of what exactly is going on.
CaH4e3, in his implementation in fceumm, says there's a 6 bit register laid out as [PP.. CCCC] at $b000. There is; on the board it's the 74ls174 labeled U4.
What I saw and what CaH4e3 wrote differs from what bunnyboy said in the nesmuseum, though. I'm not certain what to think of that.
The two PRG bits are used in an UNROM style banking fashion, with a fixed bank from $c000-$ffff and switchable from $8000-$bfff. The other two OR gates are used to select when to load the banking register: nROMSEL OR READnotWRITE OR A14. This means the register is actually mapped over the entire $8000-$bfff range. This makes up the 74ls32 labeled U7.
The 4 chr address lines through the NAND gate U6 (against PPU A12) so that the $0000-$0fff pattern table is always bank 15 and the $1000-$1fff pattern table is the two's complement of the written bank. (This is isomorphic to what CaH4e3 wrote: 0 and ($bank&15), modulo concerns about which 32kB are battery-backed.) (Also, the C bits are out of order as 3012, but it's RAM, so it doesn't matter)
This, however, leaves U5 (another '32), U8 (another '00), U9 (a '74) and U10 (a 4040).
Part of U5 and ¼ of U8 (as an inverter) is used to make the two 32kB RAMs act like one homogenous 64kB memory space, but some of the traces in the area are confusing. Another ¼ of U8 is used to prevent bus conflicts.
Jumpers: J3 vs J4 selects respectively whether one or both SRAMs are battery backed.
J1 vs J2 has something to do with how it selects the not-necessarily-battery-backed SRAM, but I can't follow the traces under U5 to figure it out.
The 4040 is a 12 bit counter IC, and its 2^12s bit (or something else, probably 2^11s bit, see traces near R2) is connected via a BJT to the cartridge edge /IRQ line. The counter is clocked by M2. Q5 also goes somewhere under the 74'74 U9. This should produce interrupts—as far as I can tell, ungatably so— at some multiple of 437 Hz.
Finally, CPU D2 is connected to the D input of one of the two D registers inside the 74'74, but I cannot figure out under what conditions it uses it. This is far enough away from the cartridge edge that there are no lower address lines than /ROMSEL, so I'm hard pressed to think of anything sensible it could be doing.
Does anyone have any insights, or a cartridge to measure?
CaH4e3, in his implementation in fceumm, says there's a 6 bit register laid out as [PP.. CCCC] at $b000. There is; on the board it's the 74ls174 labeled U4.
What I saw and what CaH4e3 wrote differs from what bunnyboy said in the nesmuseum, though. I'm not certain what to think of that.
The two PRG bits are used in an UNROM style banking fashion, with a fixed bank from $c000-$ffff and switchable from $8000-$bfff. The other two OR gates are used to select when to load the banking register: nROMSEL OR READnotWRITE OR A14. This means the register is actually mapped over the entire $8000-$bfff range. This makes up the 74ls32 labeled U7.
The 4 chr address lines through the NAND gate U6 (against PPU A12) so that the $0000-$0fff pattern table is always bank 15 and the $1000-$1fff pattern table is the two's complement of the written bank. (This is isomorphic to what CaH4e3 wrote: 0 and ($bank&15), modulo concerns about which 32kB are battery-backed.) (Also, the C bits are out of order as 3012, but it's RAM, so it doesn't matter)
This, however, leaves U5 (another '32), U8 (another '00), U9 (a '74) and U10 (a 4040).
Part of U5 and ¼ of U8 (as an inverter) is used to make the two 32kB RAMs act like one homogenous 64kB memory space, but some of the traces in the area are confusing. Another ¼ of U8 is used to prevent bus conflicts.
Jumpers: J3 vs J4 selects respectively whether one or both SRAMs are battery backed.
J1 vs J2 has something to do with how it selects the not-necessarily-battery-backed SRAM, but I can't follow the traces under U5 to figure it out.
The 4040 is a 12 bit counter IC, and its 2^12s bit (or something else, probably 2^11s bit, see traces near R2) is connected via a BJT to the cartridge edge /IRQ line. The counter is clocked by M2. Q5 also goes somewhere under the 74'74 U9. This should produce interrupts—as far as I can tell, ungatably so— at some multiple of 437 Hz.
Finally, CPU D2 is connected to the D input of one of the two D registers inside the 74'74, but I cannot figure out under what conditions it uses it. This is far enough away from the cartridge edge that there are no lower address lines than /ROMSEL, so I'm hard pressed to think of anything sensible it could be doing.
Does anyone have any insights, or a cartridge to measure?