I was looking at a pinout of the MMC2 on kevtris's page. It seems that a large number of CHR Address lines are present. But I couldn't really think of why some are. I can understand the upper address lines as they are important for determining if tile FD or FE is being read. But why are CHR A0, 1, 2, and 3 connected?
Another point I was thinking about is when tile FD or FE is fetched there are two reads that occur for reading both bit planes of the tile. But any read to the $xFDx or $xFEx areas is supposed to set or clear the latches. So how is it implemented to make sure that the switch occurs after the second read is complete? Does the hardware implement a small cycle timer or just a single delay flag or what?
I thought that if you ignore reads from $xFD0 to $xFD7 and only watch when there is a read with A3 set ($xFD8 to $xFDF) and set or clear the latch after the read is complete then you don't need any sort of timer, maybe just a delay type of flag.
Another point I was thinking about is when tile FD or FE is fetched there are two reads that occur for reading both bit planes of the tile. But any read to the $xFDx or $xFEx areas is supposed to set or clear the latches. So how is it implemented to make sure that the switch occurs after the second read is complete? Does the hardware implement a small cycle timer or just a single delay flag or what?
I thought that if you ignore reads from $xFD0 to $xFD7 and only watch when there is a read with A3 set ($xFD8 to $xFDF) and set or clear the latch after the read is complete then you don't need any sort of timer, maybe just a delay type of flag.