What is the maximum safe access delay for using EPROMs in carts?
If my math is correct, one NES clock cycle is about 560 ns. I'm not sure when the bus needs data after it asserts a chips CS line, but it seems like ~500 ns access time would be the slowest, or perhaps 500/2 for 250 ns. That's still pretty slow for EPROMs, right?
If my math is correct, one NES clock cycle is about 560 ns. I'm not sure when the bus needs data after it asserts a chips CS line, but it seems like ~500 ns access time would be the slowest, or perhaps 500/2 for 250 ns. That's still pretty slow for EPROMs, right?