Source: Brad Taylor's NTSC 2C02 tech ref
(This post implies NTSC)
I finished the CPU emulation, and heading now towards the PPU.
I'm finding the PPU render timing really complex, so I want to know if I understand it at least roughly so I can start to figure out how to implement it.
So What I understand is this:
Each CPU cycle equals 12 PPU cycles, CPU runs at 1.79 Mhz and PPU at 21.47 Mhz.
The source of timing in my emulator are the instructions that are being executed, so for each CPU cycle executed in its instructions, I advance the PPU renderer 12 cycles.
Each pixel takes 1 PPU cycle, so each scanline takes 341 PPU cycles including hblank.
There are 262 scanlines including vblank period, so a frame occurs every 89342 PPU cycles.
89342 / 12 = 7445.17, so each 7445.17 CPU cycles are executed, I trigger an NMI.
What I never saw in a doc is when I have to start counting down to the first NMI, so I guess it's from the first ever cycle executed by the CPU, that's the first cycle of the first instruction at the RESET address.
Is this right? did I get something wrong?
Thanks!
(This post implies NTSC)
I finished the CPU emulation, and heading now towards the PPU.
I'm finding the PPU render timing really complex, so I want to know if I understand it at least roughly so I can start to figure out how to implement it.
So What I understand is this:
Each CPU cycle equals 12 PPU cycles, CPU runs at 1.79 Mhz and PPU at 21.47 Mhz.
The source of timing in my emulator are the instructions that are being executed, so for each CPU cycle executed in its instructions, I advance the PPU renderer 12 cycles.
Each pixel takes 1 PPU cycle, so each scanline takes 341 PPU cycles including hblank.
There are 262 scanlines including vblank period, so a frame occurs every 89342 PPU cycles.
89342 / 12 = 7445.17, so each 7445.17 CPU cycles are executed, I trigger an NMI.
What I never saw in a doc is when I have to start counting down to the first NMI, so I guess it's from the first ever cycle executed by the CPU, that's the first cycle of the first instruction at the RESET address.
Is this right? did I get something wrong?
Thanks!