Reading what the "NMOS 65xx Instructions Set" doc says:
First PHP/PHA is mostly known as an "implied" instruction while i think its not.It is an "inmediate" one, since as we can see on cycle 2: "read the next instruction byte" and i have made some test to with decoding the byte. Anyway, thats my point of view and doesnt affect nes devlprs or nesem devlprs (i think)
What i dont know how the IC can perform 2 task in only one cycle i mean cycle 1 "fetch xxx, increment xxx" and then cycle 3 too: "Push xxx to stack, decrement xxx"
thanks in advance.
Code:
PHA, PHP
# address R/W description
--- ------- --- -----------------------------------------------
1 PC R fetch opcode, increment PC
2 PC R read next instruction byte (and throw it away)
3 $0100,S W push register on stack, decrement S
# address R/W description
--- ------- --- -----------------------------------------------
1 PC R fetch opcode, increment PC
2 PC R read next instruction byte (and throw it away)
3 $0100,S W push register on stack, decrement S
First PHP/PHA is mostly known as an "implied" instruction while i think its not.It is an "inmediate" one, since as we can see on cycle 2: "read the next instruction byte" and i have made some test to with decoding the byte. Anyway, thats my point of view and doesnt affect nes devlprs or nesem devlprs (i think)
What i dont know how the IC can perform 2 task in only one cycle i mean cycle 1 "fetch xxx, increment xxx" and then cycle 3 too: "Push xxx to stack, decrement xxx"
thanks in advance.