Hi everyone,
I came up with the first implementation of MMC3 for my emulator. Right now it has a buggy IRQ counter and can run a few games decently.
The emu passes all CPU Instructions tests, PPU vbl_nmi tests (except for the NMI_on_timing one) and PPU Vram access.
I have the following questions tough:
1. Is there any initial PRG / CHR bank setup that games expect? I can run for example Mega Man 3, SMB3, Double Dragon II, SMB2, Nintendo WC... but other games like Tiny Toon Adventures, Batman Returns and Flintstones crash on bad opcodes....
My mapper starts synced with PRG mode 0 (0x8000-0x9FFF and 0xA000-0xBFFF swappable, last bank fixed to 0xE000-0xFFFF and second-last bank in 0xC000-0xDFFF) and PPU A12 inversion bit 0 as well.
2. I tried to run Blargg's MMC3 tests, but it seems to use CHR RAM along with CHR ROM (my emu crashes on writes to the CHR area because it thinks it has only CHR ROM), how can I tell? What is the best way to implement this?
Thank you very much in advance.
I came up with the first implementation of MMC3 for my emulator. Right now it has a buggy IRQ counter and can run a few games decently.
The emu passes all CPU Instructions tests, PPU vbl_nmi tests (except for the NMI_on_timing one) and PPU Vram access.
I have the following questions tough:
1. Is there any initial PRG / CHR bank setup that games expect? I can run for example Mega Man 3, SMB3, Double Dragon II, SMB2, Nintendo WC... but other games like Tiny Toon Adventures, Batman Returns and Flintstones crash on bad opcodes....
My mapper starts synced with PRG mode 0 (0x8000-0x9FFF and 0xA000-0xBFFF swappable, last bank fixed to 0xE000-0xFFFF and second-last bank in 0xC000-0xDFFF) and PPU A12 inversion bit 0 as well.
2. I tried to run Blargg's MMC3 tests, but it seems to use CHR RAM along with CHR ROM (my emu crashes on writes to the CHR area because it thinks it has only CHR ROM), how can I tell? What is the best way to implement this?
Thank you very much in advance.