My IRQ counter code for MMC3 seems to be working well. For instance, the screen splits nicely in Super Mario 3 to allow for the game stats HUD at the bottom to be rendered independently of the scrolling level. I have not encountered any issues per se (I've yet to test MMC3 extensively on this), but I do have a question concerning the phrase "acknowledge any pending interrupts" as in the case of the IRQ disable register in MMC3
What does "acknowledge any pending interrupts" really mean? Should the MMC3 signal the CPU to do the interrupt at this point?
Thanks
Code:
IRQ disable ($E000-$FFFE, even)
7 bit 0
---- ----
xxxx xxxx
Writing any value to this register will disable MMC3 interrupts AND acknowledge any pending interrupts.
7 bit 0
---- ----
xxxx xxxx
Writing any value to this register will disable MMC3 interrupts AND acknowledge any pending interrupts.
What does "acknowledge any pending interrupts" really mean? Should the MMC3 signal the CPU to do the interrupt at this point?
Thanks