I have PPU working mostly by accident but can't fully explain it so I would like to know more about background rendering. I've read and re-read wiki on PPU rendering but still have questions, like it states that there are 2x 16 bit registers. My guess is that one is for plane0 and one for plane1. Then each tile has 2bits giving access to 8pixels for rendering?
Then Wiki states "Every 8 cycles, the bitmap data for the next tile is loaded into the upper 8 bits of this shift register. Meanwhile, the pixel to render is fetched from one of the lower 8 bits." now this doesn't make sense then as 8bits only fit 4 tiles(2bits/tile), same goes for rendering however that would mean that fineX can't be more than 3. Can anyone shed some more light on this?
Then Wiki states "Every 8 cycles, the bitmap data for the next tile is loaded into the upper 8 bits of this shift register. Meanwhile, the pixel to render is fetched from one of the lower 8 bits." now this doesn't make sense then as 8bits only fit 4 tiles(2bits/tile), same goes for rendering however that would mean that fineX can't be more than 3. Can anyone shed some more light on this?