hi, for over a year i discontinnued my work with my emulator and stopped posting (and reading).
I see new people have registered and are posting. Wich i think is good.
Well i retook the work again and i was looking the old posts. I can't find a post that says in wich cc the ppu updates things. You know, when the ppu updates/clocks its counters.
Nice to see you again!
If all else fails you can try to read Nestopia or Nintendulator's source code. I imagine they are pretty accurate in which cycle does what.
Sorry i meant that people here knows the cc and there is a post that i can't find that tell them. I don't have any problem looking at a source, but if someone points me to the right thread i will appreciate it.
Anes wrote:
I can't find a post that says in wich cc the ppu updates things. You know, when the ppu updates/clocks its counters.
Hello, welcome back. ^_^
Well, third part sources are a solid reference, but most of them have empirical things, or
spaghetti.
Anyway, as far as I know, the PPU has no internal counters. You take the 341 PPU clocks as reference, plus the scanline "counting".
Bah, try reading
here and
here.
Hi again fx3. Maybe i didn't use the correct words. To say it in other ones:
In wich scanline cc does the ppu:
1) Copy "temp" to "addr" in the prerender scanline ...
2) Gets TileX and NT low bit (H) from "temp" to "addr" ...
3) Clocks (FineY + TileY) ...
... ?
According the docs (assuming 1-341 range):
1) cc -> 1
2) cc -> 256
3) cc -> 256
is that correct?
- Please, read the linked topics again. ^_^
Anes wrote:
1) Copy "temp" to "addr" in the prerender scanline ...
304, as far as I know of.
Anes wrote:
2) Gets TileX and NT low bit (H) from "temp" to "addr" ...
256, again, for my best.
Anes wrote:
3) Clocks (FineY + TileY) ...
I'm unsure, but looks like at 252.
Ok, sorry to bother you: those cc assumming 0-340 range or 1-341 range? I think its 1-341, but i ask to be sure.
Also make sure you apply PPU writes at the end of the write cycle of an instruction, instead of just at the beginning of the instruction.
For example, STA XXXX takes 4 CPU cycles, first 3 cycles are reading the instruction and address, 4th cycle is the write. Apply the write at the end of the 4th CPU cycle, not the start of the instruction.
4 CPU cycles is an entire 12 PPU pixels in NTSC mode, and that's enough of a difference between a shaky status bar and clean graphics.
See 64doc.txt to see which cycles the writes happen on for each type of instruction.
Anes wrote:
Ok, sorry to bother you: those cc assumming 0-340 range or 1-341 range? I think its 1-341, but i ask to be sure.
There's the NTSC color burst: 341 cycles on odd frames and 340 on even frames *if* background is enabled... with a twist.