1. CPU
- I wonder about JSR or JMP instructions. If an IRQ/NMI is pending, can it be triggered right after a JSR or JMP?
2. APU
- By taking blargg's test 4 (clock jitter). My emu fails on test #3. I did a lot of debugging and I could find the reason: for some unknown way, the step 3 (0,1,2,3 mode #0) does NOT set the frameIRQ flag before a read to 4015, making the test #2 to be OK and test #3 to fail. The solution (a hack) is to check if the apu cycle counter has expired before a 4015h read - this way, the channel clock happens (on that specific cycle) & problem is fixed, but it's a hack, which I don't like to add it. I could get almost ALL the tests running OK with "hacks" to cycle counter. I'd like some advice... Tell me if unclear.
- When writting to 4017h, there's a statement about EVEN and ODD cycles. On ODD cycles, the quarter-step starts after 1 cycle, *and* mode #5 too, meaning TWO cycles of delay???
- I wonder about JSR or JMP instructions. If an IRQ/NMI is pending, can it be triggered right after a JSR or JMP?
2. APU
- By taking blargg's test 4 (clock jitter). My emu fails on test #3. I did a lot of debugging and I could find the reason: for some unknown way, the step 3 (0,1,2,3 mode #0) does NOT set the frameIRQ flag before a read to 4015, making the test #2 to be OK and test #3 to fail. The solution (a hack) is to check if the apu cycle counter has expired before a 4015h read - this way, the channel clock happens (on that specific cycle) & problem is fixed, but it's a hack, which I don't like to add it. I could get almost ALL the tests running OK with "hacks" to cycle counter. I'd like some advice... Tell me if unclear.
- When writting to 4017h, there's a statement about EVEN and ODD cycles. On ODD cycles, the quarter-step starts after 1 cycle, *and* mode #5 too, meaning TWO cycles of delay???