does the dma timer get reloaded with LUT[$4010 & f] each time it becomes zero or only when a cycle is restarted when bits remaining becomes 0 ? such that it would use the old value in $4010 till the end of the cycle when bits remaining becomes 0.
i started writing some tests here, but not sure how useful they would be to anyone as they are very basic at the moment. i could probably write a useful test but dont have any way of runnning it on the real hardware. for now i compared to other emulators. for example irq timing, assuming its exact and dma is 4 cycles. i have a long segment of nop so i can watch the program counter. i have read that sometimes dma is not 4 cycles. i have read that does not seem to be instruction related and perhaps odd/even cycles.
if a dmc dma occurs during a sprite dma, i assume that dmc interrupts sprite ? i think that was tested and no audio problems. if it does interrupt it, how many cycles does the total dma take ? i think that might be easy to test.
if the dmc is silenced, and some time later it is started, when will the first dma occer ? immdiatly or N cycles later ?
i dont expect all these to be answered yet; if they can not be then what can be doen to find out. i had some ideas for testing, but would like others input first.
also if something is not exact or unknown, then perhaps a test to verify an accepted range ?
matt
i started writing some tests here, but not sure how useful they would be to anyone as they are very basic at the moment. i could probably write a useful test but dont have any way of runnning it on the real hardware. for now i compared to other emulators. for example irq timing, assuming its exact and dma is 4 cycles. i have a long segment of nop so i can watch the program counter. i have read that sometimes dma is not 4 cycles. i have read that does not seem to be instruction related and perhaps odd/even cycles.
if a dmc dma occurs during a sprite dma, i assume that dmc interrupts sprite ? i think that was tested and no audio problems. if it does interrupt it, how many cycles does the total dma take ? i think that might be easy to test.
if the dmc is silenced, and some time later it is started, when will the first dma occer ? immdiatly or N cycles later ?
i dont expect all these to be answered yet; if they can not be then what can be doen to find out. i had some ideas for testing, but would like others input first.
also if something is not exact or unknown, then perhaps a test to verify an accepted range ?
matt