(note: I'm not using an hardware level of abstraction, so be easy)
It's pretty clear that if a CPU $4015 read and a APU frame counter clock occurs at same time, the APU status doesn't change. In other words, the APU status take effect (probably) in the next CPU clock.
Still, I don't know if the frame IRQ set at $4015 is the result of the IRQ being requested (enqueued) at that time, or only set when the CPU acknowledges it (dequeued). Well, once the CPU acknowledges the IRQ, it should trigger at the end of the current instruction. This is probably the "latency" mentioned/asked in the wiki discussion page, regarding my emu.
It's pretty clear that if a CPU $4015 read and a APU frame counter clock occurs at same time, the APU status doesn't change. In other words, the APU status take effect (probably) in the next CPU clock.
Still, I don't know if the frame IRQ set at $4015 is the result of the IRQ being requested (enqueued) at that time, or only set when the CPU acknowledges it (dequeued). Well, once the CPU acknowledges the IRQ, it should trigger at the end of the current instruction. This is probably the "latency" mentioned/asked in the wiki discussion page, regarding my emu.