Timing diagram of a LDA $xxxx instruction:
- Can an IRQ be requested and/or acknowledged during the first 3 cycles? I read somewhere about only getting triggered in the last cycle of the instruction.
- Can an IRQ (or any other flag, let's say, from $4015) be cancelled right at the 4th cycle, but before the effective read?
I have problems in a few test ROMs, like IRQ_and_DMA. Thanks.
Code:
# address R/W description
--- ------- --- ------------------------------------------
1 PC R fetch opcode, increment PC
2 PC R fetch low byte of address, increment PC
3 PC R fetch high byte of address, increment PC
4 address R read from effective address
Set CPU flags
--- ------- --- ------------------------------------------
1 PC R fetch opcode, increment PC
2 PC R fetch low byte of address, increment PC
3 PC R fetch high byte of address, increment PC
4 address R read from effective address
Set CPU flags
- Can an IRQ be requested and/or acknowledged during the first 3 cycles? I read somewhere about only getting triggered in the last cycle of the instruction.
- Can an IRQ (or any other flag, let's say, from $4015) be cancelled right at the 4th cycle, but before the effective read?
I have problems in a few test ROMs, like IRQ_and_DMA. Thanks.