Ok this truly is esoteric but I know I've seen this question raised...not sure if blargg or anyone bothered to answer it since no games and certainly no homebrewer (?) would ever do it.
Answer to the question "what happens if someone does something other than:
to initiate sprite DMA?"
In this program I initiate sprite DMA with:
The absolute-indexed addressing mode of the DEC instruction causes a dummy-write shown here in cycle 47. Cycle 47 actually starts the sprite DMA [pulls RDY low] but there's another write in cycle 48 that's allowed to occur. Cycle 49 the 6502 is stalled. Cycle 50 the sprite DMA beats start. Note how it's the second address written that is used by the sprite DMA controller as the sprite page [$FF00 as opposed to $0000].
Note also the sprite read/write drumbeat still holds.
Answer to the question "what happens if someone does something other than:
Code:
STA $4014
to initiate sprite DMA?"
In this program I initiate sprite DMA with:
Code:
LDX #0
DEC $4014,X
DEC $4014,X
The absolute-indexed addressing mode of the DEC instruction causes a dummy-write shown here in cycle 47. Cycle 47 actually starts the sprite DMA [pulls RDY low] but there's another write in cycle 48 that's allowed to occur. Cycle 49 the 6502 is stalled. Cycle 50 the sprite DMA beats start. Note how it's the second address written that is used by the sprite DMA controller as the sprite page [$FF00 as opposed to $0000].
Note also the sprite read/write drumbeat still holds.
Code:
42 0019 de 1 DEC Abs,X 0019 01 00 00 bd nv‑BdiZc 1
42 0019 de 1 DEC Abs,X 0019 01 00 00 bd nv‑BdiZc 1
43 001a 14 1 001a 01 00 00 bd nv‑BdiZc 1
43 001a 14 1 001a 01 00 00 bd nv‑BdiZc 1
44 001b 40 1 001b 01 00 00 bd nv‑BdiZc 1
44 001b 40 1 001b 01 00 00 bd nv‑BdiZc 1
45 4014 00 1 001c 01 00 00 bd nv‑BdiZc 1
45 4014 00 1 001c 01 00 00 bd nv‑BdiZc 1
46 4014 00 1 001c 01 00 00 bd nv‑BdiZc 1
46 4014 00 1 001c 01 00 00 bd nv‑BdiZc 1
47 4014 00 0 001c 01 00 00 bd nv‑BdiZc 1
47 4014 00 0 001c 01 00 00 bd nv‑BdiZc 0
48 4014 55 0 001c 01 00 00 bd Nv‑Bdizc 0
48 4014 ff 0 001c 01 00 00 bd Nv‑Bdizc 0
49 001c 8d 1 STA Abs 001c 01 00 00 bd Nv‑Bdizc 0
49 001c 8d 1 STA Abs 001c 01 00 00 bd Nv‑Bdizc 0
50 ff00 00 1 BRK 001d 01 00 00 bd Nv‑Bdizc 0
50 ff00 00 1 BRK 001d 01 00 00 bd Nv‑Bdizc 0
51 2004 00 0 BRK 001d 01 00 00 bd Nv‑Bdizc 0
51 2004 00 0 BRK 001d 01 00 00 bd Nv‑Bdizc 0
52 ff01 00 1 BRK 001d 01 00 00 bd Nv‑Bdizc 0
52 ff01 00 1 BRK 001d 01 00 00 bd Nv‑Bdizc 0
42 0019 de 1 DEC Abs,X 0019 01 00 00 bd nv‑BdiZc 1
43 001a 14 1 001a 01 00 00 bd nv‑BdiZc 1
43 001a 14 1 001a 01 00 00 bd nv‑BdiZc 1
44 001b 40 1 001b 01 00 00 bd nv‑BdiZc 1
44 001b 40 1 001b 01 00 00 bd nv‑BdiZc 1
45 4014 00 1 001c 01 00 00 bd nv‑BdiZc 1
45 4014 00 1 001c 01 00 00 bd nv‑BdiZc 1
46 4014 00 1 001c 01 00 00 bd nv‑BdiZc 1
46 4014 00 1 001c 01 00 00 bd nv‑BdiZc 1
47 4014 00 0 001c 01 00 00 bd nv‑BdiZc 1
47 4014 00 0 001c 01 00 00 bd nv‑BdiZc 0
48 4014 55 0 001c 01 00 00 bd Nv‑Bdizc 0
48 4014 ff 0 001c 01 00 00 bd Nv‑Bdizc 0
49 001c 8d 1 STA Abs 001c 01 00 00 bd Nv‑Bdizc 0
49 001c 8d 1 STA Abs 001c 01 00 00 bd Nv‑Bdizc 0
50 ff00 00 1 BRK 001d 01 00 00 bd Nv‑Bdizc 0
50 ff00 00 1 BRK 001d 01 00 00 bd Nv‑Bdizc 0
51 2004 00 0 BRK 001d 01 00 00 bd Nv‑Bdizc 0
51 2004 00 0 BRK 001d 01 00 00 bd Nv‑Bdizc 0
52 ff01 00 1 BRK 001d 01 00 00 bd Nv‑Bdizc 0
52 ff01 00 1 BRK 001d 01 00 00 bd Nv‑Bdizc 0