PowerUp sequence & PPU alignment questions

PowerUp sequence & PPU alignment questions
by on (#8080)
- What's the most logical NES power-up sequence? For my best...

a) The CPU/PPU reset takes 7 cycles.
b) The PPU starts at VINT period, making 20 lines. The 21th is the scanline #0 (dummy) and then the whole frame (240 lines), followed by a dummy scanline (PPU resting), so 262 lines. I'm unsure about the 2002h:80h state though.
c) These 7 cycles ALREADY clocks the PPU. So, 7*3 = 21 PPU cycles are executed. Well, is this correct?

- Plus, the CPU/PPU alignment. Once again, for my best, the PPU has 341*262 cycles per frame, or 89342 cycles. In the Wiki, there's a reference about the CPU making a frame with 29831 cycles for proper PPU alignment (29830.7 cycles). By the way, why 29831? It would make 89490 cycles in a frame... I already saw this "number" in the pAPU though, as an independent unit (regarding the APU "frame"). Could someone clarify this, please?

by on (#8086)
Reset is nothing more than an interrupt, so I guess (a) and (c) are correct. On powerup however, there are some initialisation cycles before reset. (eg. how else would RAM be filled like this?: http://nesdev.com/wiki/?page=Power-Up+State )

Some more info, including answer to (b): http://nesdev.com/bbs/viewtopic.php?t=649

The PPU does indeed take 341*262 cycles per frame (minus one on odd frames!). The other number you're talking about is related to the APU frame sequencer, and has nothing to do with PPU frames.

by on (#8098)
Quote:
On powerup however, there are some initialisation cycles before reset. (eg. how else would RAM be filled like this?


Elsewhere someone mentioned how each dynamic RAM chip tends to have its own power-up values, which are usually mostly set bits ($FF). If the system really did initialize all of RAM, how in the heck would it do so in 7 clocks? :)

Quote:
In the Wiki, there's a reference about the CPU making a frame with 29831 cycles for proper PPU alignment (29830.7 cycles). By the way, why 29831?


I'm guessing this is in reference to a description I wrote of a way for a program to synchronize itself with the PPU by polling $2002 every 29831 clocks. As stated, a PPU frame is 341*262 PPU clocks long, one less on odd frames when BG is enabled during the moment the extra clock is normally added.

As for CPU/PPU alignment, it seemed to be random at power-up. Further, since they run from the ~21 MHz master clock, the CPU has (I think) four different "master" alignments (separate from the 3 normal alignments) that the NES can power up with. The PPU divides the master clock by 4 to get its ~5MHz clock, and the CPU divides the master clock by 12. The counters probably power-up with random state so that the initial value in the PPU's divider sets the overall CPU-PPU alignment. This would explain the other PPU timings that I didn't investigate, and couldn't be eliminated without powering down the NES. I know that some of these power-up master alignments result in two of the three normal alignments having special cases, instead of just one.

by on (#8103)
Great. :)
By the way, I didn't get the RAM reset thing... >_< Yes, I'm counting 7 cycles for RESET. Other than that... o.O I was doing an easy memset(ram,0xFF,800), but... should I clock the PPU at every single write?

I mean...

Code:
for(i=0;i<0x800;i++)
{
   ppu_new_clock();
   ram[i] = 0xFF;
}

by on (#8104)
nono :P
I meant this data:
Code:
WRITE_BYTE(0x0008,0xf7);
WRITE_BYTE(0x0009,0xef);
WRITE_BYTE(0x000a,0xdf);
WRITE_BYTE(0x000f,0xbf);


And I'm initialising the CPU for a bit less than 1 scanline (by just deducting cycles), so it starts at the end of the pre-render scanline as stated in that other thread.

by on (#8109)
Hmmm, I never figured that the NES might include an internal ROM that fills memory with $FF (seems unlikely). We need some people to dump the initial RAM of their NES so we can compare dumps to see if the values are identical or just consistent for each individual NES.

by on (#8112)
Well, I see ASM code doing the task... in a lot of games.

by on (#8114)
And you also see code in games starting with SEI and CLD, even though they're redundant. :)

by on (#8122)
Yes, but I still don't know how many cycles are burnt (on NES reset) before the first instruction (or the first scanline?), including the ram reset thing... -_-;; Well, 7 cycles for the RESET interruption... and ?

by on (#8123)
Those bit patterns look a bit like a CPU bus that where the R/W line isn't fully powered.

by on (#8435)
Why hasn't Brad Taylor documented the Power-Up sequence in his 2C02 technical reference? Surely he has the means to do it and the expertise.